View MAX1358B_2019162.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the MAX1358B smart data-acquisition system (das) is based on a 16-bit, sigma-delta analog-to-digital converter (adc) and system- support functionality for a micro- processor (?)-based system. this device integrates an adc, dacs, operational amplifiers, internal selec- table-voltage reference, temperature sensors, analog switches, a 32khz oscillator, a real-time clock (rtc) with alarm, a high-frequency-locked loop (fll) clock, four user-programmable i/os, an interrupt generator, and 1.8v and 2.7v voltage monitors in a single chip. the MAX1358B has dual 10:1 differential input multiplex- ers (muxes) that accept signal levels from 0 to av dd . an on-chip 1x to 8x programmable-gain amplifier (pga) allows measuring low-level signals and reduces external circuitry required. the MAX1358B operates from a single +1.8v to +3.6v supply and consumes only 1.15ma in normal mode and only 3? in sleep mode. the MAX1358B has two dacs with one uncommitted op amp. the serial interface is compatible with either spi/qspi or microwire, and is used to power up, configure, and check the status of all functional blocks. the MAX1358B is available in a space-saving, 40-pin tqfn package and is specified over the commercial (0 c to +70 c) and the extended (-40 c to +85 c) tem- perature ranges. applications battery-powered and portable devices electrochemical and optical sensors medical instruments industrial control data-acquisition systems features +1.8v to +3.6v single-supply operation multichannel, 16-bit, sigma-delta adc 10sps to 477sps programmable conversion rate self- and system offset and gain calibration pga with gains of 1, 2, 4, or 8 unipolar and bipolar modes 10-input differential multiplexer 10-bit force-sense dacs uncommitted op amps dual spdt and spst analog switches selectable references 1.25v, 2.048v, and 2.5v internal charge pump system support rtc and alarm register internal/external temperature sensor internal oscillator with clock output user-programmable i/o and interrupt generator v dd monitors spi/qspi/microwire, 4-wire serial interface space-saving (6mm x 6mm x 0.8mm), 40-pin tqfn package MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ________________________________________________________________ maxim integrated products 1 19-5159; rev 0; 8/10 for pricing delivery, and ordering information please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. 40 *exposed pad. *ep 39 38 37 36 35 34 33 32 31 21 22 23 24 25 26 27 28 29 30 cpout in1+ in1- outb swb swa fba outa agnd fbb ain2 ain1 ref reg av dd cf- cf+ dv dd dgnd upio1 11 12 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 1 + clk upio2 upio3 upio4 dout sclk din int clk32k 32kout 32kin sno1 scm1 snc1 out1 snc2 scm2 sno2 cs reset tqfn top view MAX1358B pin configuration ordering information part temp range pin-package MAX1358Bctl+ 0 c to +70 c 40 tqfn-ep* MAX1358Betl+ -40 c to +85 c 40 tqfn-ep* + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = dv dd = +1.8v to +3.6v, v ref = +1.25v, external reference, f clk32k = 32.768khz (external clock), c reg = 10?, c cpout = 10?, 10? between cf+ and cf-, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd .........................................................-0.3v to +4v dv dd to dgnd.........................................................-0.3v to +4v av dd to dv dd ............................................................-4v to +4v agnd to dgnd.....................................................-0.3v to +0.3v clk32k to dgnd ....................................-0.3v to (dv dd + 0.3v) upio_ to dgnd........................................................-0.3v to +4v digital inputs to dgnd ............................................-0.3v to +4v analog inputs to agnd ...........................-0.3v to (av dd + 0.3v) digital output to dgnd........................-0.3v to (dv dd + 0.3v) analog outputs to agnd.........................-0.3v to (av dd + 0.3v) cpout........................................................(dv dd - 0.3v) to +4v continuous current into any pin.........................................50ma continuous power dissipation (t a = +70 c) 40-pin tqfn (derate 25.6mw/ c above +70 c) ....2051.3mw operating temperature range MAX1358Bctl+ .................................................0 c to +70 c MAX1358Betl+ ..............................................-40 c to +85 c junction temperature ......................................................+150? storage temperature range .............................-65 c to +150 c soldering temperature (reflow) .......................................+260 c parameter symbol conditions min typ max units adc dc accuracy noise-free resolution data rate = 10sps, pga gain = 2; data rate = 10sps to 60sps, pga gain = 1; no missing codes, table 1 (note 2) 16 bits conversion rate no missing codes, table 1 10 477 sps output noise no missing codes table 1 integral nonlinearity inl unipolar mode, av dd = 3v, pga gain = 1, data rate = 40sps 0.0046 %fsr uncalibrated 1.0 unipolar offset error or bipolar zero error (note 3) pga gain = 1, calibrated, t a = +25 c, data rate = 10sps 0.003 %fsr bipolar 1 unipolar offset-error or bipolar zero-error temperature drift (note 4) unipolar 1 ?/ c uncalibrated 0.6 gain error (notes 3, 5) pga = 1, calibrated, data rate = 10sps 0.003 %fsr gain-error temperature coefficient (notes 4, 6) 2 ppm/ c dc positive power-supply rejection ratio psrr pga gain = 1, unipolar mode, measured by full-scale error with av dd = 1.8v to 3.6v 85 db adc analog inputs (ain1, ain2) dc input common-mode rejection ratio cmrr pga gain = 1, unipolar mode 85 db datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = dv dd = +1.8v to +3.6v, v ref = +1.25v, external reference, f clk32k = 32.768khz (external clock), c reg = 10?, c cpout = 10?, 10? between cf+ and cf-, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units normal-mode 60hz rejection ratio pga gain = 1, unipolar mode, data rate = 40sps (note 2) 100 db normal-mode 50hz rejection ratio data rate = 10sps or 40sps, pga gain = 1, unipolar mode (note 2) 100 db absolute input range v agnd av dd v unipolar mode -0.05/ gain v ref / gain differential input range bipolar mode -v ref / gain v ref / gain v adc not in measurement mode, mux enabled, t a +55 c, inputs = +0.1v to (av dd - 0.1v) 1 dc input current (note 7) t a = +85 c 5 na input sampling capacitance c in 5 pf input sampling rate f sample 21.94 khz external source impedance at input table force-sense dac (r l = 10k and c l = 200pf, fba = outa, unless otherwise noted) resolution guaranteed monotonic 10 bits differential nonlinearity dnl code 3d hex to 3ff hex 1 lsb integral nonlinearity inl code 3d hex to 3ff hex 4 lsb offset error reference to code 52 hex 20 mv offset-error tempco 5 v/ c gain error excludes offset and voltage reference error 5 lsb gain-error tempco excludes offset and reference drift 5.6 ppm/ c input leakage current at swa/b switches open (notes 7, 8) 1 na t a = -40 c to +85 c 1 na t a = 0 c to +70 c 600 input leakage current at fba/b v fba = +0.3v to (av dd - 0.3v) (note 7) t a = 0 c to +50 c 400 pa dac output buffer leakage current dac buffer disabled (note 7) 75 na input common-mode voltage at fba 0 av dd - 0.35 v line regulation av dd = +1.8v to +3.6v, t a = +25 c 40 175 v/v load regulation i out = 2ma, c l = 1000pf 0.5 v/a output voltage range v agnd av dd v datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 4 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = +1.8v to +3.6v, v ref = +1.25v, external reference, f clk32k = 32.768khz (external clock), c reg = 10?, c cpout = 10?, 10? between cf+ and cf-, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units output slew rate 52 hex to 3ff hex code swing rising or falling, r l = 10k , c l = 100pf 50 v/ms output-voltage settling time 10% to 90% rising or falling to 0.5 lsb 65 s f = 0.1hz to 10hz 40 input-voltage noise referred to fba, excludes reference noise f = 10hz to 10khz 100 v p-p outa shorted to agnd 20 output short-circuit current outa shorted to av dd 18 ma input-output swa/swb switch resistance between sw_ and out_, hfclk enabled 150 swa/swb switch turn-on/off time hfclk enabled 100 ns power-on time excluding reference 12 s external reference (ref) input voltage range v agnd av dd v input resistance dac on, internal ref and adc off 2.5 m dc input leakage current internal ref, dac, and adc off (note 7) 100 na internal voltage reference (c ref = 4.7f) av dd +1.8v, t a = +25 c 1.213 1.25 1.288 av dd +2.2v, t a = +25 c 1.987 2.048 2.109 reference output voltage v ref av dd +2.7v, t a = +25 c 2.425 2.5 2.575 v t a = -40 c to +85 c 25 output-voltage temperature coefficient (note 7) tc t a = 0 c to +70 c 13 ppm/ o c ref shorted to agnd 65 ma output short-circuit current i rsc ref shorted to av dd 90 a line regulation 25 v/v i source = 0 to 500a 1.2 load regulation t a = +25 c, v ref = 1.25v i sink = 0 to 50a 1.7 v/a datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor _______________________________________________________________________________________ 5 electrical characteristics (continued) (av dd = dv dd = +1.8v to +3.6v, v ref = +1.25v, external reference, f clk32k = 32.768khz (external clock), c reg = 10?, c cpout = 10?, 10? between cf+ and cf-, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units long-term stability (note 9) 150 ppm/ 1000hrs f = 0.1hz to 10hz, av dd = 3v 50 output noise voltage f = 10hz to 10khz, av dd = 3v 200 ? p-p turn-on settling time buffer only, settle to 0.1% of final value 100 ? temperature sensor temperature measurement resolution 10sps 0.11 c/lsb t a = 0 c to +50 c 0.5 internal temperature-sensor measurement error (note 10) external voltage reference, two- current method t a = -40 o c to +85 c 1 c t a = +25 c 0.5 t a = 0 c to +50 c 0.5 external temperature-sensor measurement error (note 11) t a = -40 c to +85 c 1.0 c temperature measurement noise 0.18 c rms temperature measurement power-supply rejection ratio 0.2 c/v op amp input offset voltage v os v cm = 0.5v 1 15 mv offset-error tempco 6.2 ?/ o c t a = -40 c to +85 c 0.006 1na t a = 0 c to +70 c4 300 in1+ t a = 0 c to +50 c2 200 pa t a = -40 c to +85 c 0.025 1na t a = 0 c to +70 c20 600 input bias current (note 7) i bias in1- t a = 0 c to +50 c 400 pa input offset current i os v in 1 _ = + 0.3v to ( av d d - 0.3v ) ( n ote 7) 1na input common-mode voltage range cmvr 0 av d d - 0.35 v 0 v c m 75mv 60 75mv < v c m av d d - 0.5v, t a = +25? 60 75 common-mode rejection ratio cmrr av d d - 0.5v v c m av d d - 0.35v 75 db datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 6 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = +1.8v to +3.6v, v ref = +1.25v, external reference, f clk32k = 32.768khz (external clock), c reg = 10?, c cpout = 10?, 10? between cf+ and cf-, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units power-supply rejection ratio psrr av dd = +1.8v to +3.6v, t a = +25c 76.5 100 db large-signal voltage gain a vol 100mv v out_ av dd - 100mv (note 12) 90 116 db i source = 10a 0.005 i source = 50a 0.025 i source = 100a 0.05 i source = 500a 0.25 sourcing i source = 2ma 0.5 i sink = 10a 0.005 i sink = 50a 0.025 i sink = 100a 0.05 i sink = 500a 0.25 output-voltage drop v out sinking i sink = 2ma 0.5 v gain bandwidth product gbw unity-gain configuration, c l = 1nf 80 khz phase margin unity-gain configuration, c l = 1nf (note 12) 60 degrees output slew rate sr c l = 200pf 0.05 v/s f = 0.1hz to 10hz 50 input-voltage noise unity-gain configuration f = 10hz to 10khz 100 v p-p v out_ shorted to agnd 20 output short-circuit current v out_ shorted to av dd 18 ma power-on time 12 s spdt switches (sno_, snc_, scm_, hfclk enabled) v scm_ = 0v t a = 0c to +50c 45 v scm_ = 0.5v t a = 0c to +50c 50 on-resistance r on v scm_ = 0.5v to av dd t a = -40 c to +85 c 150 t a = -40 c to +85 c 1 na t a = 0 c to +70 c 600 sno_, snc_ off-leakage current i sno_(off) i snc_(off) v sno_ , v snc_ = +0.5v, +1.5v; v scm_ = +1.5v, +0.5v (note 7) t a = 0 c to +50 c 400 pa t a = -40 c to +85 c 2 t a = 0 c to +70 c 1.2 scm_ off-leakage current i scm_(off) v sno_ , v snc_ = +0.5v, +1.5v; v scm_ = +1.5v, +0.5v (note 7) t a = 0 c to +50 c 0.8 na t a = -40 c to +85 c 2 t a = 0 c to +70 c 1.2 scm_ on-leakage current i scm_(on) v sno_ , v snc_ = +0.5v, +1.5v, or unconnected; v scm_ = +1.5v, +0.5v (note 7) t a = 0 c to +50 c 0.8 na input voltage range v agnd av dd v turn-on/off time t on /t off break-before-make 100 ns datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor _______________________________________________________________________________________ 7 electrical characteristics (continued) (av dd = dv dd = +1.8v to +3.6v, v ref = +1.25v, external reference, f clk32k = 32.768khz (external clock), c reg = 10?, c cpout = 10?, 10? between cf+ and cf-, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units input capacitance sno_, snc_, or scm_ = av dd or agnd; switch connected to enabled mux input 2.5 pf charge pump maximum output current i out 10 ma no load 3.2 3.3 3.6 output voltage i out = 10ma 3.0 v output-voltage ripple i out = 10ma, excluding esr of external capacitor 50 mv p-p load regulation i out = 10ma, excluding esr of external capacitor 15 20 mv/ma reg input voltage range internal linear regulator disabled 1.6 1.8 v reg input current linear regulator off, charge pump off 3 na cpout input voltage range charge pump disabled 1.8 3.6 v cpout input leakage current charge pump disabled 2 na signal-detect comparator tsel[2:0] = 0 hex 0 tsel[2:0] = 4 hex 50 tsel[2:0] = 5 hex 100 tsel[2:0] = 6 hex 150 differential input-detection threshold voltage tsel[2:0] = 7 hex 200 mv differential input-detection threshold error 10 mv common-mode input voltage range v agnd av dd v turn-on time 45 s voltage monitors dv dd monitor supply voltage range for valid reset 1.4 3.6 v trip threshold (dv dd falling) 1.80 1.85 1.95 v dv dd monitor timeout reset period 1.5 s hyse bit set to logic 1 225 dv dd monitor hysteresis hyse bit set to logic 0 40 mv datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 8 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = +1.8v to +3.6v, v ref = +1.25v, external reference, f clk32k = 32.768khz (external clock), c reg = 10?, c cpout = 10?, 10? between cf+ and cf-, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units dv dd monitor turn-on time 5ms cpout monitor supply voltage range 1.4 3.6 v cpout monitor trip threshold 2.7 2.8 2.9 v cpout monitor hysteresis 35 mv cpout monitor turn-on time 5ms internal power-on reset voltage 1.7 v 32khz oscillator (32kin, 32kout) clock frequency dv dd = 2.7v 32.768 khz stability dv dd = 1.8v to 3.6v, excluding crystal 25 ppm oscillator startup time 1500 ms crystal load capacitance 6pf low-frequency clock input/output (clk32k) output clock frequency 32.768 khz absolute input to output clock jitter cycle to cycle 5 ns input to output rise/fall time 10% to 90%, 30pf load 5 ns input duty cycle 40 60 % output duty cycle 54 % high-frequency clock output (clk) f out = f fll 4.8660 4.9152 4.9644 f out = f fll /2, power-up default 2.4330 2.4576 2.4822 f out = f fll /4 1.2165 1.2288 1.2411 mhz fll output clock frequency f out = f fll /8 608.25 614.4 620.54 khz cycle to cycle, fll off 0.1 absolute clock jitter cycle to cycle, fll on 0.5 ns rise and fall time t r /t f 10% to 90%, 30pf load 10 ns f out = 4.9152mhz 40 60 duty cycle f out = 2.4576mhz, 1.2288mhz, 614.4khz 45 55 % uncalibrated clk frequency error fll calibration not performed 35 % digital inputs (sclk, din, cs , upio_, clk32k) input high voltage v ih 0.7 x dv dd v input low voltage v il 0.3 x dv dd v datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor _______________________________________________________________________________________ 9 electrical characteristics (continued) (av dd = dv dd = +1.8v to +3.6v, v ref = +1.25v, external reference, f clk32k = 32.768khz (external clock), c reg = 10?, c cpout = 10?, 10? between cf+ and cf-, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units dv dd supply voltage 0.7 x dv dd upio_ input high voltage cpout supply voltage 0.7 x v cpout v dv dd supply voltage 0.3 x dv dd upio_ input low voltage cpout supply voltage 0.3 x v cpout v input hysteresis v hys dv dd = 3.0v 200 mv input current i in v in = v dgnd or dv dd (note 7) 0.01 100 na input capacitance v in = v dgnd or dv dd 4 pf v in = dv dd or v cpout , pullup enabled 0.01 1 upio_ input current v in = dv dd or v cpout or 0v, pullup disabled 1 a upio_ pullup current v in = 0v, pullup enabled, unconnected upio_ inputs are pulled up to dv dd or cpout with pullup enabled 0.1 2 5 a digital outputs (dout, reset , upio_, clk32k, int, clk) output low voltage v ol i sink = 1ma 0.4 v output high voltage v oh i source = 500a 0.8 x dv dd v dout three-state leakage current i l 0.01 1 a dout three-state output capacitance c out 4.5 pf reset output low voltage v ol i sink = 1ma 0.4 v reset output leakage current open-drain output, reset deasserted (note 7) 0.1 a i sink = 1ma, upio_ referenced to dv dd 0.4 upio_ output low voltage v ol i sink = 4ma, upio_ referenced to cpout 0.4 v i source = 500a, upio_ referenced to dv dd 0.8 x dv dd upio_ output high voltage v oh i source = 4ma, upio_ referenced to cpout v cpout - 0.4 v power requirement analog supply voltage range av dd 1.8 3.6 v digital supply voltage range dv dd 1.8 3.6 v datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 10 ______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = +1.8v to +3.6v, v ref = +1.25v, external reference, f clk32k = 32.768khz (external clock), c reg = 10?, c cpout = 10?, 10? between cf+ and cf-, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units av dd = dv dd = 3.6v 1.2 2.0 i max everything on, charge pump unloaded, no digital pins, sinking/sourcing current, e.g., rst , upio_, and clk32k, max internal temp- sensor current, clock output buffers unloaded, adc at 477sps av dd = dv dd = 2.7v 1.15 1.4 total supply current i normal all on except charge pump and temp sensor, adc at 477sps, clk output buffer enabled, clock output buffers unloaded 1.15 1.5 ma av dd = dv dd = 2.7v 3.0 5.2 t a = -40c to +85c av dd = dv dd = 3.6v 6.7 av dd = dv dd = 2.7v 3.0 sleep-mode supply current (i avdd + i dvdd ) i sleep t a = +25c av dd = dv dd = 3.6v 4.5 a t a = -40c to +85c 2.5 shutdown supply current (i avdd + i dvdd ) i shdn all off t a = +25c 1.2 a note 1: devices are production tested at t a = room temperature. specifications to t a = -40? and t a = +85? are guaranteed by design. note 2: guaranteed by design or characterization. note 3: the offset and gain errors are corrected by self-calibration or system calibration. for accurate calibrations, perform cali- bration at the lowest rate. the calibration error is therefore in the order of peak-to-peak noise for the selected rate. note 4: eliminate drift errors by recalibration at the new temperature. note 5: the gain error excludes reference error, offset error (unipolar), and zero error (bipolar). note 6: gain-error drift does not include unipolar-offset drift or bipolar zero-error drift. it is effectively the drift of the part if zero- scale error is removed. note 7: these specifications are obtained from characterization during design or from initial product evaluation. not production tested or guaranteed. note 8: v outa = +0.5v or +1.5v, v swa = +1.5v or +0.5v, t a = 0 c to +50 c. note 9: long-term stability is characterized using five to six parts. the bandgaps are turned on for 1000hrs at room temperature with the parts running continuously. daily measurements are taken and any obvious outlying data points are discarded. note 10: temperature error is the difference in the calculated temperature using the internal circuit vs. measurements made using precision external voltage and current meters. the same diode and diode equation are used for both measurements. note 11: all the stated temperature accuracies assume that 1) the external diode characteristic is precisely known (i.e., ideal) and 2) the adc reference voltage is exactly equal to 1.25v. any variations to this known reference characteristic and voltage caused by temperature, loading, or power supply results in errors in the temperature measurement. the actual tempera- ture calculation is performed externally by the ?. note 12: values based on simulation results and are not production tested or guaranteed. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 11 output noise (? rms ) rate (sps) gain = 1 gain = 2 gain = 4 gain = 8 10 1.75 1.75 1.75 1.75 40 2.92 2.92 2.92 2.92 50 3.23 3.23 3.23 3.23 60 3.60 3.60 3.60 3.60 200 56.06 56.06 56.06 56.06 240 102.36 102.36 102.36 102.36 400 587.06 587.06 587.06 587.06 477 951.07 951.07 951.07 951.07 table 1. output noise (notes 13 and 14) note 13: v ref = +1.25v, bipolar mode, v in = 1.24912v, pga gain = 1, t a = +25?. note 14: assume ? sigma peak-to-peak variation; noise-free resolution means no code flicker at given bits?lsb. peak-to-peak resolution (bits) rate (sps) gain = 1 gain = 2 gain = 4 gain = 8 10 17.57 16.57 15.57 14.57 40 16.83 15.83 14.83 13.83 50 16.68 15.68 14.68 13.68 60 16.53 15.53 14.53 13.53 200 12.57 11.57 10.57 9.57 240 11.70 10.70 9.70 8.70 400 9.18 8.18 7.18 6.18 477 8.48 7.48 6.48 5.48 table 2. peak-to-peak resolution external capacitance (pf) parameter 0 (note 15) 50 100 500 1000 5000 resistance (k ? ) 350 60 30 10 4 1 table 3. maximum external source impedance without 16-bit gain error note 15: 2pf parasitic capacitance is assumed, which represents pad and any other parasitic capacitance. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 12 ______________________________________________________________________________________ timing characteristics (figures 1 and 19) (av dd = dv dd = +1.8v to +3.6v, external v ref = +1.25v, f clk32k = 32.768khz (external clock), c reg = 10?, c cpout = 10?, 10? between cf+ and cf-, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units sclk operating frequency f sclk 0 10 mhz sclk cycle time t cyc 100 ns sclk pulse-width high t ch 40 ns sclk pulse-width low t cl 40 ns din to sclk setup t ds 30 ns din to sclk hold t dh 0 ns sclk fall to dout valid t do c l = 50pf, figure 2 40 ns cs fall to dout enable t dv c l = 50pf, figure 2 48 ns cs rise to dout disable t tr c l = 50pf, figure 2 48 ns cs to sclk rise setup t css 20 ns cs to sclk rise hold t csh 0 ns dv dd monitor timeout period t dslp (note 16) 1.5 s wake-up (wu) pulse width t wu minimum pulse width required to detect a wake-up event 1 s shutdown delay t dpu the delay for shdn to go high after a valid wake-up event 1 s the turn-on time for the high-frequency clock and fll (flle = 1) (note 17) 10 ms hfclk turn-on time t dfon if flle = 0, the turn-on time for the high- frequency clock (notes 7, 18) 10 s crdy to int delay t dfi the delay for crdy to go low after the hfclk clock output has been enabled (note 19) 7.82 ms hfclk disable delay t dfof the delay after a shutdown command has asserted and before hfclk is disabled (note 20) 1.95 ms shdn assertion delay t dpd (note 21) 2.93 ms note 16: the delay for the sleep voltage monitor output, reset , to go high after v dd rises above the reset threshold. this is largely driven by the startup of the 32khz oscillator. note 17: flle is gated by an and function with three inputs?he external reset signal, the internal dv dd monitor output, and the external shdn signal. the time delay is timed from the internal lov dd going high or the external reset going high, whichever happens later. hfclk always starts in the low state. note 18: if flle = 0, the internal signal crdy is not generated by the fll block and int or int is deasserted. note 19: crdy is used as an interrupt signal to inform the ? that the high-frequency clock has started. only valid if flle = 1. note 20: t dfof gives the ? time to clean up and go into sleep-override mode properly. note 21: t dpd is greater than the hfclk delay to clean up before losing power. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 13 t ds t css t dh t dv t do t tr cs sclk din dout t csh t cyc t ch t cl t csh figure 1. detailed serial-interface timing dv dd c load = 50pf 6k ? dout a) for enable, high impedance to v oh and v ol to v oh for disable, v oh to high impedance b) for enable, high impedance to v ol and v oh to v ol for disable, v ol to high impedance dout 6k ? c load = 50pf figure 2. dout enable and disable time load circuits typical operating characteristics (dv dd = av dd = 1.8v, v ref = +1.25v, c cpout = 10?, t a = +25 c, unless otherwise noted.) supply current vs. supply voltage MAX1358B toc01 av dd , dv dd (v) i dvdd i avdd supply current (ma) 3.3 3.0 2.7 2.4 2.1 0.5 0.6 0.7 0.8 0.9 1.0 0.4 1.8 3.6 all on with adc at 477sps and maximum internal temp-sensor current setting dv dd supply current vs. dv dd supply voltage MAX1358B toc02 dv dd (v) supply current (a) 3.3 3.0 2.7 2.4 2.1 0.010 0.100 1.000 10.000 0.001 1.8 3.6 sleep mode: all off except 32khz osc, rtc, and 1.8v monitor shutdown mode: all off shutdown mode sleep mode datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 14 ______________________________________________________________________________________ typical operating characteristics (continued) (dv dd = av dd = 1.8v, v ref = +1.25v, c cpout = 10?, t a = +25 c, unless otherwise noted.) av dd supply current vs. av dd supply voltage MAX1358B toc03 supply voltage (v) supply current (a) 3.3 3.0 2.7 2.4 2.1 0.4 0.8 1.2 1.6 2.0 0 1.8 3.6 sleep mode: all off except 32khz osc, rtc, and 1.8v monitor shutdown mode: all off sleep mode shutdown mode dv dd supply current vs. temperature MAX1358B toc04 temperature (c) supply current (ma) 60 35 10 -15 0.6 0.7 0.8 0.9 1.0 0.5 -40 85 all on with adc at 512sps and maximum internal temp-sensor current setting dv dd = 3.0v dv dd = 1.8v dv dd supply current vs. temperature MAX1358B toc05 temperature (c) supply current (ma) 60 35 10 -15 1.0 1.5 2.0 2.5 3.0 0.5 -40 85 sleep mode: all off except 32khz osc, rtc, and 1.8v monitor dv dd = 3.0v dv dd = 1.8v dv dd supply current vs. temperature MAX1358B toc06 temperature ( c) supply current (na) 60 35 10 -15 4 8 12 16 20 0 -40 85 dv dd = 3.0v dv dd = 1.8v all off av dd supply current vs. temperature MAX1358B toc07 temperature (c) supply current (ma) 60 35 10 -15 0.47 0.49 0.51 0.53 0.55 0.45 -40 85 all on with adc at 512sps and maximum internal temp-sensor current setting dv dd = 3.0v dv dd = 1.8v av dd supply current vs. temperature MAX1358B toc08 temperature (c) supply current (ma) 60 35 10 -15 0.9 1.3 1.7 2.1 2.5 0.5 -40 85 sleep mode: all off except 32khz osc, rtc, and 1.8v monitor dv dd = 3.0v dv dd = 1.8v av dd supply current vs. temperature MAX1358B toc09 temperature (c) supply current (a) 60 35 10 -15 0.25 0.30 0.35 0.40 0.45 0.50 0.20 -40 85 all off dv dd = 3.0v dv dd = 1.8v internal oscillator frequency vs. temperature MAX1358B toc10 temperature (c) oscillator frequency (mhz) 60 35 10 -15 2.35 2.40 2.45 2.50 2.55 2.60 2.30 -40 85 fll enabled fll disabled datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 15 typical operating characteristics (continued) (dv dd = av dd = 1.8v, v ref = +1.25v, c cpout = 10?, t a = +25 c, unless otherwise noted.) internal oscillator frequency vs. supply voltage MAX1358B toc11 av dd , dv dd supply voltage (v) internal oscillator frequency (mhz) 3.3 3.0 2.1 2.4 2.7 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.20 1.8 3.6 fll enabled fll disabled clk = 2.4576mhz reference output voltage vs. supply voltage MAX1358B toc12 supply voltage (v) reference output voltage (v) 3.3 3.0 2.7 2.4 2.1 1.5 2.0 2.5 3.0 1.0 1.8 3.6 50k i load v ref = 2.50v v ref = 1.25v v ref = 2.048v reference output voltage vs. output current MAX1358B toc13 output current (a) reference output voltage (v) 450 350 250 150 50 1.2494 1.2496 1.2498 1.2500 1.2502 1.2492 -50 550 v ref = 1.25v reference output voltage vs. output current MAX1358B toc14 output current (a) reference output voltage (v) 450 350 250 150 50 2.0488 2.0490 2.0492 2.0494 2.0496 2.0486 -50 550 v ref = 2.048v reference output voltage vs. output current MAX1358B toc15 output current (a) reference output voltage (v) 450 350 250 150 50 2.4962 2.4964 2.4966 2.4968 2.4970 2.4960 -50 550 v ref = 2.5v reference output voltage vs. temperature MAX1358B toc16 temperature (c) reference output voltage (v) 60 35 10 -15 1.246 1.247 1.248 1.249 1.250 1.251 1.245 -40 85 v ref = 1.25v reference output voltage vs. temperature MAX1358B toc17 temperature (c) reference output voltage (v) 60 35 10 -15 2.044 2.046 2.048 2.050 2.052 2.042 -40 85 v ref = 2.048v reference output voltage vs. temperature MAX1358B toc18 temperature (c) reference output voltage (v) 60 35 10 -15 2.488 2.491 2.494 2.497 2.500 2.485 -40 85 v ref = 2.5v reference drift (0?c to 50?c) MAX1358B toc18b absolute drift (ppm/ n c) occurrences 26 21 16 11 6 v ref = 1.25v box method datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 16 ______________________________________________________________________________________ typical operating characteristics (continued) (dv dd = av dd = 1.8v, v ref = +1.25v, c cpout = 10?, t a = +25 c, unless otherwise noted.) reference voltage output noise (0.1hz to 10hz) MAX1358B toc19 50v/div ac-coupled 1s/div reference noise density vs. frequency MAX1358B toc20 frequency (hz) noise (nv/ hz) 100 1000 10 100 1000 1 10 10,000 v ref = 1.25v adc inl vs. output code MAX1358B toc21 output code inl (lsb) 60k 50k 40k 30k 20k 10k -0.008 -0.006 -0.004 -0.002 0 0.002 -0.010 0 70k v ref = 2.048v unipolar mode gain = 1 60sps adc inl vs. output code MAX1358B toc22 output code inl (lsb) 60k 50k 30k 40k 20k 10k -0.004 -0.003 -0.002 -0.001 0 0.001 0.002 0.003 0.004 0.005 -0.005 070k av dd = dv dd = 1.8v v ref = 1.25v bipolar mode gain = 1 60sps adc maximum inl vs. supply voltage MAX1358B toc23 supply voltage (v) adc maximum inl (%) 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 -0.0056 -0.0052 -0.0048 -0.0044 -0.0040 -0.0060 2.7 3.6 v ref = 2.048v unipolar mode gain = 1 60sps adc maximum inl vs. supply voltage MAX1358B toc24 supply voltage (v) adc maximum inl (%) 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 -0.0021 -0.0022 -0.0023 -0.0024 -0.0025 -0.0020 1.8 3.6 v ref = 1.25v bipolar mode gain = 1 60sps adc maximum inl vs. temperature MAX1358B toc25 temperature ( n c) adc maximum inl (%) 60 35 10 -15 -0.006 -0.005 -0.004 -0.003 -0.002 -0.001 0 -0.007 -40 85 v ref = 2.048v unipolar mode gain = 1 60sps adc maximum inl vs. temperature MAX1358B toc26 temperature ( n c) adc maximum inl (%) 60 35 10 -15 0.0005 0.0010 0.0015 0.0020 0.0025 0.0030 0 -40 85 v ref = 1.25v bipolar mode gain = 1 60sps datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 17 typical operating characteristics (continued) (dv dd = av dd = 1.8v, v ref = +1.25v, c cpout = 10?, t a = +25 c, unless otherwise noted.) adc maximum inl vs. common-mode input voltage MAX1358B toc27 common-mode voltage (v) adc maximum inl (%) 2.0 1.8 1.4 1.6 1.0 1.2 0.8 -0.0045 -0.0040 -0.0035 -0.0030 -0.0025 -0.0020 -0.0015 -0.0010 -0.0005 0 -0.0050 0.6 2.2 v ref = 1.25v bipolar mode gain = 1 60sps MAX1358B toc28 adc maximum vs. output data rate data rate (sps) adc maximum inl (%) 400 300 200 100 0.005 0.010 0.015 0.020 0.025 0.030 0 0500 av dd = dv dd = 1.8v v ref = 1.25v bipolar mode gain = 1 adc maximum inl vs. pga gain MAX1358B toc29 adc maximum inl (%) 8 6 4 2 0.002 0.004 0.006 0.008 0.010 0 0 pga gain av dd = dv dd = 1.8v v ref = 1.25v bipolar mode 60sps adc offset error vs. temperature MAX1358B toc30 temperature ( n c) adc offset error (%) 60 35 10 -15 -0.0005 0 0.0005 0.0010 0.0015 0.0020 -0.0010 -40 85 v ref = 2.048v unipolar mode gain = 1 60sps adc gain error vs. temperature MAX1358B toc31 temperature ( n c) adc gain error (%) 60 35 10 -15 0.001 0.002 0.003 0.004 0.005 0.006 0 -40 85 v ref = 2.048v unipolar mode gain = 1 60sps adc offset error vs. supply voltage MAX1358B toc32 supply voltage (v) offser error (%fsr) 3.4 3.2 2.0 2.2 2.4 2.8 2.6 3.0 0 0.0005 0.0010 0.0015 0.0020 0.0025 0.0030 0.0035 -0.0005 1.8 3.6 v ref = 1.25v unipolar mode gain = 1 60sps adc gain error vs. supply voltage MAX1358B toc33 supply voltage (v) gain error (%fsr) 3.4 3.2 2.0 2.2 2.4 2.8 2.6 3.0 0.0005 0.0010 0.0015 0.0020 0.0025 0.0030 0.0035 0.0040 0 1.8 3.6 v ref = 1.25v unipolar mode gain = 1 60sps adc mux input dc current vs. temperature MAX1358B toc34 temperature ( n c) input current (na) 60 35 10 -15 0.010 0.100 1.000 10.00 100.00 1000.00 0.001 -40 85 ain1 = av dd /2 mux+ = ain1 mux- = agnd adc converting adc off datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 18 ______________________________________________________________________________________ typical operating characteristics (continued) (dv dd = av dd = 1.8v, v ref = +1.25v, c cpout = 10?, t a = +25 c, unless otherwise noted.) ain_ leakage current vs. input voltage MAX1358B toc35 v ain_ (v) input current (na) 2.5 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -0.5 03.0 t a = +85c t a = +25c t a = +55c sw_ leakage current vs. input voltage MAX1358B toc36 v sw_ (v) input current (na) 2.5 2.0 1.5 1.0 0.5 -0.2 -0.1 0 0.1 0.2 0.3 0.4 -0.3 03.0 t a = +85c t a = +25c t a = +55c out_ = av dd /2 fb leakage current vs. input voltage MAX1358B toc37 v fb (v) input current (na) 2.5 2.0 1.5 1.0 0.5 -0.2 -0.1 0 0.1 0.2 0.3 0.4 -0.3 03.0 t a = +85c t a = +25c t a = +55c sno_ leakage current vs. input voltage MAX1358B toc38 v sno_ (v) input current (na) 2.5 2.0 0.5 1.0 1.5 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 -0.20 03.0 scm_ = av dd /2 t a = +85c t a = +25c t a = +55c snc_ leakage current vs. input voltage MAX1358B toc39 v snc_ (v) input current (na) 2.5 2.0 0.5 1.0 1.5 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 -0.20 03.0 scm_ = av dd /2 t a = +85c t a = +25c t a = +55c scm_ leakage current vs. input voltage MAX1358B toc40 v scm_ (v) input current (na) 2.5 2.0 0.5 1.0 1.5 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 -0.20 03.0 sn0_ = snc_ = av dd /2 t a = +85c t a = +25c t a = +55c in1- leakage current vs. input voltage MAX1358B toc41 v in1- (v) input current (na) 2.5 2.0 0.5 1.0 1.5 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 -0.20 03.0 t a = +85 n c t a = +55 n c t a = +25 n c dac inl vs. output code MAX1358B toc42 output code inl (lsb) 1000 900 700 800 200 300 400 500 600 100 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 1100 av dd = 1.8v v ref = 1.25v datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 19 typical operating characteristics (continued) (dv dd = av dd = 1.8v, v ref = +1.25v, c cpout = 10?, t a = +25 c, unless otherwise noted.) dac inl vs. output code m ax1358b toc43 output code inl (lsb) 1000 900 700 800 200 300 400 500 600 100 -0 . 4 -0 . 3 -0 . 2 -0 . 1 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 -0 . 5 0 1100 v ref = 2.048v dac dnl vs. output code m ax1358b toc44 output code inl (lsb) 1000 900 700 800 200 300 400 500 600 100 -0 . 4 -0 . 3 -0 . 2 -0 . 1 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 -0 . 5 0 1100 av dd = 1.8v v ref = 1.25v dac dnl vs. output code m ax1358b toc45 output code inl (lsb) 1000 900 700 800 200 300 400 500 600 100 -0 . 4 -0 . 3 -0 . 2 -0 . 1 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 -0 . 5 0 1100 v ref = 2.048v dac output voltage vs. analog supply voltage m ax1358b toc46 avdd (v) dac output voltage (v) 3.3 3.0 2.1 2.4 2.7 0.62385 0.62390 0.62395 0.62400 0.62405 0.62410 0.62415 0.62420 0.62380 1.8 3.6 v ref = 1.25v code = 0x200 r load = 10k i dac output voltage vs. temperature MAX1358B toc47 temperature (c) dac output voltage (v) 60 35 10 -15 0.6234 0.6238 0.6242 0.6246 0.6250 0.6230 -40 85 v ref = 1.25v external code = 0x200 r load = 10k i av dd = dv dd = 1.8v 60 35 10 -15 -40 85 0 50 100 150 200 250 -50 temperature (c) input current (pa) dac fb_ input bias current vs. temperature m ax1358b toc48 fb_ = av dd fb_ = 0 dac gain error vs.temperature MAX1358B toc49 temperature (c) gain error (lsb) 60 35 -15 10 -0.2 -0.1 0 0.1 0.3 0.2 0.4 0.5 -0.3 -40 85 v ref = 1.25v external av dd = dv dd = 1.8v offset measured at code 0x52 v ref = 2.5v external av dd = dv dd = 3.0v dac output noise (0.1hz to 10hz) MAX1358B toc50 20v/div ac-coupled 1s/div ref = 1.25v av dd = dv dd = 1.8v code = 0x3ff datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 20 ______________________________________________________________________________________ typical operating characteristics (continued) (dv dd = av dd = 1.8v, v ref = +1.25v, c cpout = 10?, t a = +25 c, unless otherwise noted.) frequency (khz) 10.00 1.00 0.10 0.01 100.00 dac output-noise density vs. frequency m ax1358b toc51 noise (nv/ hz) 10 100 1000 1 v ref = 1.25v av dd = dv dd = 1.8v code = 3ff dac large-signal step response (0x052 to 0x3ff) MAX1358B toc52 500mv/div 2v/div sclk outa 0v 10s/div out_ = fb_ dac large-signal step response (0x3ff to 0x052) MAX1358B toc53 500mv/div sclk outa 0v 10s/div out_ = fb_ op-amp input offset voltage vs. temperature MAX1358B toc54 temperature (c) offset voltage (mv) 60 35 10 -15 -0.4 -0.3 -0.2 -0.1 0 -0.5 -40 85 v cm = 0.5v op-amp input offset histogram offset (mv) occurrences 5 10 15 20 25 30 35 0 -2.92 -2.62 -2.32 -2.02 -1.72 -1.42 -1.12 -0.82 -0.52 -0.22 0.08 0.38 0.68 0.98 1.28 m ax1358b toc55 op-amp output voltage vs. load current MAX1358B toc56 load current (ma) op-amp output voltage (v) 1.5 1.0 0 0.5 -1.0 -0.5 -1.5 0.89952 0.89954 0.89956 0.89958 0.89960 0.89962 0.89964 0.89966 0.89968 0.89970 0.89950 -2.0 2.0 unity gain v in = 0.9v av dd = dv dd = 1.8v op-amp output voltage vs. load current MAX1358B toc57 load current (ma) op-amp output voltage (v) 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 1.49945 1.49950 1.49955 1.49960 1.49965 1.49970 1.49940 -2.0 2.0 unity gain v in = 1.5v av dd = dv dd = 3.0v datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 21 typical operating characteristics (continued) (dv dd = av dd = 1.8v, v ref = +1.25v, c cpout = 10?, t a = +25 c, unless otherwise noted.) op-amp output voltage vs. temperature MAX1358B toc58 temperature (c) output voltage (v) 60 35 10 -15 0.8982 0.8983 0.8984 0.8985 0.8986 0.8987 0.8981 -40 85 unity gain av dd = dv dd = 1.8v v in+ = av dd /2 r load = 10k i op-amp output voltage vs. supply voltage MAX1358B toc59 supply voltage (v) op-amp output voltage (v) 3.4 3.2 2.0 2.2 2.4 2.8 2.6 3.0 0.49965 0.49970 0.49975 0.49980 0.49985 0.49990 0.49995 0.50000 0.49960 1.8 3.6 unity gain v in = 0.5v r load = 10k i op-amp output noise (0.1hz to 10hz) MAX1358B toc60 20v/div ac-coupled 1s/div unity gain v in1+ = 0.5v av dd = dv dd = 1.8v frequency (khz) 10.00 1.00 0.10 0.01 100.00 op-amp output-noise density vs. frequency m ax1358b toc61 noise (nv/ hz) 10 100 1000 1 v in+ = 0.5v av dd = dv dd = 1.8v unity gain op-amp unity-gain input range MAX1358B toc62 v in (v) v out - v in (mv) 3.0 2.4 1.8 1.2 0.6 -8 -6 -4 -2 0 2 4 6 8 10 -10 03.6 av dd = dv dd = 3.6v unity gain no load closed-loop op-amp gain and phase vs. frequency m ax1358b toc63 frequency (hz) gain (db) phase () 100k 10k 100 1k -60 -40 -20 0 20 40 60 80 180 135 90 45 0 -45 -90 -135 -180 -80 10 1 m closed-loop gain = 1000 r load = 10k i c load = 200pf phase gain spdt on-resistance vs. scm_ voltage MAX1358B toc64 v scm_ (v) r on ( i ) 2.5 2.0 1.5 1.0 0.5 25 30 35 40 45 20 0 3.0 i scm_ = 1ma av dd = 3v av dd = 1.8v spst on-resistance vs. sw_ voltage MAX1358B toc65 v sw_ (v) r on ( i ) 2.5 2.0 1.5 1.0 0.5 40 45 50 55 60 65 70 35 03.0 i sw_ = 1ma av dd = 1.8v av dd = 3v datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 22 ______________________________________________________________________________________ spdt on-resistance vs. temperature MAX1358B toc66 temperature (c) r on ( i ) 60 35 10 -15 20 30 40 50 10 -40 85 v scm_ = av dd i scm_ = 1ma av dd = dv dd = 3.0v av dd = dv dd = 1.8v spdt on-resistance vs. temperature MAX1358B toc67 temperature (c) r on ( i ) 60 35 10 -15 40 50 60 70 30 -40 85 v scm_ = av dd i scm_ = 1ma av dd = dv dd = 3.0v av dd = dv dd = 1.8v spst leakage current vs. temperature m ax1358b toc68 leaka g e c urrent ( na ) 0.010 0.100 1.000 0.001 v in = av dd 60 35 10 -15 -40 85 temperature (c) spdt switching time vs. supply voltage MAX1358B toc69 av dd , dv dd (v) t on t off time (ns) 3.3 3.0 2.7 2.4 2.1 30 40 50 60 70 20 1.8 3.6 spst switching time vs. supply voltage MAX1358B toc70 av dd , dv dd (v) t on t off time (ns) 3.3 3.0 2.7 2.4 2.1 30 40 50 60 70 20 1.8 3.6 spdt/spst switching time vs. temperature MAX1358B toc71 temperature (c) switching time (ns) 60 35 10 -15 10 20 30 40 50 0 -40 85 t on t off r load = 1k i c load = 35pf typical operating characteristics (continued) (dv dd = av dd = 1.8v, v ref = +1.25v, c cpout = 10?, t a = +25 c, unless otherwise noted.) internal temperature sensor error vs. ambient temperature m ax1358b toc72 temperature sensor error (c) -1.5 -1.0 -0.5 0 1.0 0.5 1.5 2.0 -2.0 v ref = 1.250v 60 35 10 -15 -40 85 temperature (c) internal temperature sensor error vs. reference voltage m ax1358b toc73 reference voltage (v) temperature sensor error (c) 1.27 1.25 1.23 -10 -5 0 5 10 15 -15 1.21 1.29 t a = +85c t a = +27c t a = -40c datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 23 voltage supervisor threshold vs. temperature MAX1358B toc74 temperature (c) voltage threshold (v) 60 35 10 -15 1.8 2.1 2.4 2.7 3.0 1.5 -40 85 cpout supervisor dv dd supervisor falling charge-pump output voltage vs. output current MAX1358B toc75 output current (ma) charge-pump output voltage (v) 8 6 4 2 3.1 3.2 3.3 3.4 3.5 3.0 010 av dd = dv dd = 1.8v charge-pump output voltage vs. temperature MAX1358B toc76 temperature (c) output voltage (v) 60 35 10 -15 3.14 3.18 3.22 3.26 3.30 3.10 -40 85 av dd = dv dd = 1.8v i load = 10ma typical operating characteristics (continued) (dv dd = av dd = 1.8v, v ref = +1.25v, c cpout = 10?, t a = +25 c, unless otherwise noted.) charge-pump output resistance vs. capacitance m ax1358b toc77 capacitance (f) output resistance ( i ) 20 15 10 5 20 40 60 80 100 0 025 av dd = dv dd = 1.8v i out = 10ma charge-pump output-voltage ripple vs. output current MAX1358B toc78 output current (ma) charge-pump output-voltage ripple (mv p-p ) 8 6 4 2 10 20 30 40 50 0 010 av dd = dv dd = 1.8v datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 24 ______________________________________________________________________________________ pin name function 1 clk clock output. default is 2.457mhz output clock for the c. 2 upio2 user-programmable input/output 2. see the upio2_ctrl register section for functionality. 3 upio3 user-programmable input/output 3. see the upio3_ctrl register section for functionality. 4 upio4 user-programmable input/output 4. see the upio4_ctrl register section for functionality. 5 dout serial-data output. data is clocked out on sclks falling edge. high impedance when cs is high, when upio/spi pass-through mode is enabled, dout mirrors the state of upio1. 6 sclk serial-clock input. clocks data in and out of the serial interface. 7 din serial-data input. data is clocked in on sclks rising edge. 8 cs active-low chip-select input. data is not clocked into din unless cs is low. when cs is high, dout is high impedance. high impedance when cs is high; when upio/spi pass-through mode is enabled, dout mirrors the state of upio1. 9 int programmable active-high/low interrupt output. adc, upio wake-up, alarm, and voltage-monitor events. 10 clk32k 32khz clock input/output. outputs 32khz clock for the c. can be programmed as an input by enabling the io32e bit to accept an external 32khz input clock. the rtc, pwm, and watchdog timer always use the internal 32khz clock derived from the 32khz crystal. 11 reset active-low, open-drain reset output. remains low while dv dd is below the 1.8v voltage threshold and stays low for a timeout period (t dslp ) after dv dd rises above the 1.8v threshold. reset also pulses low when the watchdog timer times out and holds low during por until the 32khz oscillator stabilizes. 12 32kout 32khz crystal output. connect an external 32khz watch crystal between 32kin and 32kout. 13 32kin 32khz crystal input. connect an external 32khz watch crystal between 32kin and 32kout. 14 sno1 analog switch 1 normally open terminal. analog input to mux. 15 scm1 analog switch 1 common terminal. analog input to mux. 16 snc1 analog switch 1 normally closed terminal. analog input to mux (open on por). 17 sno2 analog switch 2 normally open terminal. analog input to mux. 18 scm2 analog switch 2 common terminal. analog input to mux (open on por). 19 snc2 analog switch 2 normally closed terminal. analog input to mux. 20 out1 amplifier 1 output. analog input to mux. 21 in1- amplifier 1 inverting input. analog input to mux. 22 in1+ amplifier 1 noninverting input pin description datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 25 pin name function 23 swa daca spst s hunt switch input. connects to outa through an spst switch. 24 fba daca force-sense feedback input. analog input to mux. 25 outa daca force-sense output. analog input to mux. 26 agnd analog ground 27 av dd analog supply voltage. also adc reference voltage during av dd measurement. bypass to agnd with 10f and 0.1f capacitors in parallel as close to the pin as possible. 28 swb dacb spst s hunt switch input. connects to outb through an spst switch. 29 fbb dacb force-sense feedback input. analog input to mux. 30 outb force-sense dacb ouput. analog input to mux. 31 ain2 analog input 2. analog input to mux. inputs have internal programmable current source for external temperature measurement. 32 ain1 analog input 1. analog input to mux. inputs have internal programmable current source for external temperature measurement. 33 ref reference input/output. output of the reference buffer amplifier or external reference input. disabled at power-up to allow external reference. reference voltage for adc and dacs. 34 reg linear voltage-regulator output. charge-pump-doubler input voltage. bypass reg with a 10f capacitor to dgnd for charge-pump regulation. 35 cf- 36 cf+ charge-pump flying capacitor terminals. connect an external 10f (typ) capacitor between cf+ and cf-. 37 cpout charge-pump output. connect an external 10f (typ) reservoir capacitor between cpout and dgnd. there is a low threshold diode between dv dd and cpout. when the charge pump is disabled, cpout is pulled up within 300mv (typ) of dv dd . 38 dv dd digital supply voltage. bypass to dgnd with 10f and 0.1f capacitors in parallel as close to the pin as possible. 39 dgnd digital ground. also ground for cascaded linear voltage regulator and charge-pump doubler. 40 upio1 user-programmable input/output 1. see the upio1_ctrl register for functionality. ep exposed pad. leave unconnected or connect to agnd. pin description (continued) datasheet.in
MAX1358B detailed description the MAX1358B das features a multiplexed differential 16-bit adc, 10-bit force-sense dacs, an rtc with an alarm, a selectable bandgap voltage reference, a signal- detect comparator, 1.8v and 2.7v voltage monitors, and wake-up control circuitry, all controlled by a 4-wire serial interface (see figure 3 for the functional diagram). the das directly interfaces to various sensor outputs and, once configured, provides the stimulus, signal con- ditioning, and data conversion, as well as ? support. see the applications section for sample MAX1358B applications. the 16-bit adc features programmable continuous con- version rates as shown in table 4, and gains of 1, 2, 4, and 8 (table 5) to suit applications with different power 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 26 ______________________________________________________________________________________ temp sensor ref agnd outa outb scm2 out1 agnd ref in1- fbb scm1 fba ain1 sno1 snc1 temp+ temp- sno2 snc2 ain2 10:1 mux neg 10:1 mux pos a v = 1, 2, 4, 8 v/v polarity flipper prog. v os pga a v = 1, 1.6384, 2 v/v upio dgnd agnd av dd dv dd serial interface din cs dout sclk 1.25v bandgap ref 16-bit adc in+ in- ref op1 10-bit dac outa ref fba buf swa 10-bit dac outb ref fbb buf swb pga out1 sno1 snc1 scm1 cmp upio1 upio2 upio3 upio4 32.768khz oscillator 32kin 32kout watchdog timer 4.9152mhz hf oscillator and fll clk clk32k ain2 ain1 interrupt int pwm clk32k input/output control dv dd (1.8v) voltage monitor rtc and alarm sno2 snc2 scm2 charge- pump doubler cf+ cf- in1- in1+ prog current source temp+ temp- 32k ain2 ain1 cpout (2.7v) voltage monitor linear 1.65v voltage regulator cpout reg status 4 reset ldvd ald crdy sdc add adou upr<4:1> 4 upf<4:1> lcpd 16 control logic hfclk m32k m32k m32k hfclk wdto dv dd MAX1358B spdt1 spdt2 figure 3. functional diagram datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 27 and dynamic range constraints. the force-sense dac provides 10-bit resolution for precise sensor applica- tions. the adc and dacs both utilize a low-drift 1.25v internal bandgap reference for conversions and full- scale range setting. the rtc has a 138-year range and provides an alarm function that can be used to wake up the system or cause an interrupt at a predefined time. the power-supply voltage monitor detects when dv dd falls below a trip threshold voltage of +1.8v and asserts reset . the MAX1358B uses a 4-wire serial interface to communicate directly among spi, qspi, or microwire devices for system configuration and readback functions. analog-to-digital converter (adc) the MAX1358B includes a sigma-delta adc with pro- grammable conversion rate, a pga, and a dual 10:1 input mux. when performing continuous conversions at 10sps or single conversions at the 40sps setting (effec- tively 10sps due to four sample sigma-delta settling), the adc has 16-bit noise-free resolution. the noise-free resolution drops to 10 bits at the maximum sampling rate of 477sps. differential inputs support unipolar (between 0 and v ref ) and bipolar (between ? ref ) modes of operation. note: avoid combinations of input signal and pga gains that exceed the reference range at the adc input. the adou bit in the status register indicates if the adc has overranged or underranged. zero-scale and full-scale calibrations remove offset and gain errors. direct access to gain and zero-scale cali- bration registers allows system-level offset and gain cal- ibration. the zero-scale adjustment register allows intentional positive offset skewing to preserve unipolar- mode resolution for signals that have a slight negative offset (i.e., unipolar clipping near zero can be removed). perform adc calibration whenever the adc configura- tion, temperature, or av dd changes. the adc-done sta- tus can be programmed to provide an interrupt on int or on any upio_. pga gain an integrated pga provides four selectable gains (+1v/v, +2v/v, +4v/v, and +8v/v) to maximize the dynamic range of the adc. bits gain1 and gain0 set the gain (see the adc register for more information). the pga gain is implemented in the digital filter of the adc. adc modulator the MAX1358B performs analog-to-digital conversions using a single-bit, 3rd-order, switched-capacitor sigma- delta modulator. the sigma-delta modulation converts the input signal into a digital pulse train whose average duty cycle represents the digitized signal information. the pulse train is then processed by a digital decimation filter. the modulator provides 2nd-order frequency shap- ing of the quantization noise resulting from the single-bit quantizer. the modulator is fully differential for maximum signal-to-noise ratio and minimum susceptibility to power-supply noise. signal-detect comparator int asserts (and remains asserted) within 30? when the differential voltage on the selected analog inputs exceeds the signal-detect comparator trip threshold. the signal-detect comparator? differential input trip threshold (i.e., offset) is user selectable and can be pro- grammed to the following values: 0mv, 50mv, 100mv, 150mv, or 200mv. analog inputs the adc provides two external analog inputs: ain1 and ain2. the rail-to-rail inputs accept differential or single-ended voltages, or external temperature-sensing diodes. the unused op amps, switches, or dac inputs and output pins can also be used as rail-to-rail analog inputs if the associated function is disabled. analog input protection internal protection diodes clamp the analog inputs to av dd and agnd and allow the channel input to swing from (agnd - 0.3v) to (av dd + 0.3v). for accurate conversions near full scale, the inputs must not exceed av dd by more than 50mv or be lower than agnd by 50mv. if the inputs exceed (agnd - 0.3v) to (av dd + 0.3v), limit the current to 50ma. analog mux the MAX1358B includes a dual 10:1 mux for the positive and negative inputs of the adc. figure 3 illustrates which signals are present at the inputs of each mux for the MAX1358B. the muxp[3:0] and muxn[3:0] bits of the mux register select the input to the adc and the signal- detect comparator (tables 8 and 9). see the mux register description in the register definitions section for multi- plexer functionality. the pol bit of the adc register swaps the polarity of mux output signals to the adc. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 28 ______________________________________________________________________________________ digital filtering the MAX1358B contains an on-chip digital lowpass fil- ter that processes the data stream from the modulator using a sinc 4 (sinx/x) 4 response. the sinc 4 filter has a settling time of four output data periods (4 x 200ms). the MAX1358B has 25% overrange capability built into the modulator and digital filter: figure 4 shows the filter frequency response. the sinc 4 characteristic -3db cutoff frequency is 0.228 times the first notch frequency. the output data rate for the digital filter corresponds with the positioning of the first notch of the filter? fre- quency response. the notches of the sinc 4 filter are repeated at multiples of the first notch frequency. the sinc 4 filter provides an attenuation of better than 100db at these notches. for example, 50hz is equal to five times the first notch frequency and 60hz is equal to six times the first notch frequency. force-sense dac the MAX1358B incorporates two 10-bit force-sensing dacs. the dacs?reference voltage sets the full-scale range. program the daca_op register using the serial interface to set the output voltages of the dac at outa. connecting resistors in a voltage-divider configuration between outa, fba, and gnd sets a different closed- loop gain for the output amplifier (see the applications information section). the dac output amplifier typically settles to ?.5 lsb from a full-scale transition within 65? (unity gain and loaded with 10k ? in parallel with 200pf). loads of less than 1k ? could degrade performance. see the typical operating characteristics for the source-and-sink capability of the dac output. the MAX1358B features a software-programmable shutdown mode for the dac. power down daca or dacb independently or simultaneously by clearing the dae and dbe bits (see the daca_op register and dacb_op register sections). dac output outa and outb go high impedance when powered down. the dacs are normally powered down at power-on reset. charge pump the charge pump provides > 3v at cpout with a maxi- mum 10ma load. enable the charge pump through the ps_vmons register. the charge pump is powered from dv dd . see figures 5 and 6 for block diagrams of the charge pump and linear regulator. the charge pump is disabled at power-on reset. an internal clock drives the charge-pump clock and adc clock. the charge pump delivers a maximum 10ma of current to external devices. the droop and the ripple depend on the clock frequency (f clk = 32.768khz/2), switch resistances (r switch = 5 ? ), and the external capacitors (10?) along with their respec- tive esrs, as shown below. vir r fc r esr esr v i fc i esr droop out out out clk f switch c c ripple out clk cpout out c f cpout cpout = =+ ++ =+ 1 24 2 hf n sin n f f sin f f m m () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 4 frequency (hz) gain (db) 100 80 60 40 20 -160 -120 -80 -40 0 -200 0 120 figure 4. filter frequency response datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 29 voltage supervisors the MAX1358B provides voltage supervisors to monitor dv dd and cpout. the first supervisor monitors the dv dd supply voltage. reset asserts and sets the corre- sponding ldvd status bit when dv dd falls below the 1.8v threshold voltage. when the dv dd supply voltage rises above the threshold during power-up, reset deasserts after a nominal 1.5s timeout period to give the crystal oscillator time to stabilize. set the threshold hys- teresis using the hyse bit of the ps_vmons register. see the ps_vmons register section for configuring hys- teresis. there is no separate voltage monitor for av dd , but the analog supply is covered by the dv dd monitor in many applications where dv dd and av dd are externally connected together. multiple supply applications where av dd and dv dd are not connected together require a separate external voltage monitor for av dd . see figure 7 for a block diagram of the dv dd voltage supervisor. the second voltage monitor tracks the charge-pump output voltage, cpout. if cpout falls below the 2.7v threshold, a corresponding register status bit (lcpd) is set to flag the condition. the cpout monitor output can also be mapped to the interrupt generator and out- put on int. the cpout monitor can be used as a 3v av dd monitor in applications where the charge pump is disabled and cpout is connected to av dd . av dd must be greater or equal to dv dd when cpout is used to monitor av dd. see figure 8 for a block diagram of the cpout voltage supervisor. interrupt generator (int) the interrupt generator provides an interrupt to an external ?. the source of the interrupt is generated by the status register and can be masked and unmasked through the imsk register. crdy is unmasked by default, and int is active-high at power-on reset. int is programmable as active-high and active-low. possible sources include a rising or falling edge of upio_, an rtc alarm, an adc conversion completion, or the volt- age-supervisor outputs. the interrupt causes int to assert when configured as an interrupt output. op 1.22v 1.65v linear 1.65v voltage regulator dv dd reg ldoe ldoe figure 5. linear-regulator block diagram cf+ cf- cpout reg m32k charge-pump doubler nonoverlap clock generator cpe figure 6. charge-pump block diagram datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 30 ______________________________________________________________________________________ crystal oscillator the on-chip oscillator requires an external crystal (or resonator) connected between 32kin and 32kout with a 32.768khz operating frequency. this oscillator is used for the rtc, alarm, pwm, watchdog, charge pump, and fll. in any crystal-based oscillator circuit, the oscillator frequency is sensitive to the capacitive load (c l ). c l is the capacitance that the crystal needs from the oscillator circuit and not the capacitance of the crystal. the input capacitance across 32kin and 32kout is 6pf. choose a crystal with a 32.768khz oscillation frequency and a 6pf capacitive load such as the c-002rx32-e from epson crystal. using a crys- tal with a c l that is larger than the load capacitance of the oscillator circuit causes the oscillator to run faster than the specified nominal frequency of the crystal or to not start up. see figures 9 and 10 for block diagrams of the crystal oscillator and the clk32k i/o. real-time clock (rtc) the integrated rtc provides the current time information from a 32-bit counter and subsecond counts from an 8-bit ripple counter. an internally generated reference clock of 256hz (derived from the 32.768khz crystal) dri- ves the 8-bit subsecond counter. an overflow of the 8-bit subsecond counter inputs a 1hz clock to increment the 32-bit second counter. the rtc 32-bit second counter is translatable to calendar format with firmware. all 40 bits (32-bit second counter and 8-bit subsecond counter) must be clocked in or out for valid data. the rtc and the 32.768khz crystal oscillator consume less than 1? when the rest of the device is powered down. time-of-day alarm program the al_day register with a 20-bit value, which corresponds to a time 1s to 12 days later than the cur- rent time with a 1s resolution. the alarm status bit, ald, asserts when the 20 bits of the al_day register match- es the 20 lsbs of the 32-bit second counter. the ade bit automatically clears when the time-of-day alarm trips. the time-of-day alarm causes the device to exit sleep mode. cmp analog 2:1 mux control logic reset dv dd 1.25v 1.8vth 2.0vth ldvd lsde lsde hyse por rste dv dd (1.8v) voltage monitor wdto figure 7. dv dd voltage-supervisor block diagram cmp cpout 1.25v 2.7vth lcpd cpde cpde cpout (2.7v) voltage monitor figure 8. cpout voltage-supervisor block diagram datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 31 watchdog enable the watchdog timer by writing a 1 to the wde bit in the clk_ctrl register. after enabling the watch- dog timer, the device asserts reset for 250ms, if the watchdog address register is not written every 500ms. due to the asynchronous nature of the watchdog timer, the watchdog timeout period varies between 500ms and 750ms. write a 0 to the wde bit to disable the watchdog timer. see figure 11 for a block diagram of the watchdog timer. high-frequency clock an internal oscillator and an fll are used to generate a 4.9152mhz ?% high-frequency clock. this clock and derivatives are used internally by the adc, analog switches, and pwm. this clock signal outputs to clk. when the fll is enabled, the high- frequency clock is locked to the 32.768khz reference. if the fll is dis- abled, the high-frequency clock is free-running. at power-up, the clk pin defaults to a 2.4576mhz clock output, which is compatible with most ?s. see figure 12 for a block diagram of the high-frequency clock. user-programmable i/os the MAX1358B provides four digital programmable i/os (upio1?pio4). configure upios as logic inputs or outputs using the upio control register. configure the internal pullups using the upio setup register, if required. at power-up, the upios are internally pulled up to dv dd . upio_ outputs can be referenced to dv dd or cpout. see the upio__ctrl register and upio_spi register sections for more details on config- uring the upio_ pins. 32kin 32kout 32.768khz oscillator 32khz oscillator osce 32k figure 9. 32khz crystal-oscillator block diagram io32e clk32k ck32e osce clk32k i/o control 2:1 mux 1 0 io32e io32e 32k m32k figure 10. clk32k i/o block diagram d q q r ck d q q r ck divide- by-8192 32k wde por wdw watchdog timer por pulses high during power-up. wdw pulses high during watchdog register write. 4hz wdto figure 11. watchdog timer block diagram datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 32 ______________________________________________________________________________________ program each upio1?pio4 as one of the following: general-purpose input power-mode control analog switch (spst) and spdt control input adc data-ready output general-purpose output pwm output alarm output spi pass-through internal and external (remote) temperature sensors an internal transistor or a remote transistor (or diode) is used with the adc and a programmable current source to measure the ambient temperature. depending on the method, either two or four currents are passed through the pn junction. the voltage across the pn junction is measured at each current. for each current, the voltage across a series resistor is also measured. measuring the voltage across the resistor allows the user to determine the precise current ratios. a microcontroller can then use the diode equation to calculate the temperature. the four-current method eliminates errors caused by parasitic resistance in series with the diode, which increases the apparent voltage across the pn junction. when measuring temperature using the internal transis- tor for a sensor, the two-current method is usually ade- quate although the four-current method can also be used. refer to application note 4296: measuring temperature with the max1358 data acquisition system for details on the measurement procedure. m32k tune<8:0> hfce flle crdy hfclk 1, 2, 4, 8 divider 2:1 mux clk clke cksel<1:0> cksel2 1 0 4.9152mhz hf oscillator and fll 4.9152mhz 32.768khz frequency compare freq error digitally controlled oscillator frequency integrator figure 12. high-frequency clock and fll block diagram figure 13. temperature-sensor measurement block diagram current source 1:3 demux ival<1:0> imux<1:0> ain1 ain2 ain1 ain2 temp+ temp- programmable current source temp sensor datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 33 the temperature equations for the two-current and four- current methods are as follows: two-current method: t = q(v be2 - v be1 )/(n k ln(v r2 /v r1 )) four-current method: t = q(v be2 + v be3 - v be1 - v be4 )/(n k ln((v r2 x v r3 )/(v r1 x v r4 )) where t is the temperature in degrees kelvin, v bex is the base to emitter voltage at current x, v rx is the volt- age across the current-sensing resistor at current x, q is the charge on an electron, k is boltzmann? constant, and n is the ideality factor for the diode. from a practi- cal standpoint, it is easiest to combine all the constants into one constant that also includes the voltage resolu- tion of the adc in unipolar mode. this requires intro- ducing the term v ref , which is the reference voltage of the adc. an n prefix on a term indicates that it is the integer value read directly from the adc. two-current method: t = 0.1771 x v ref (n vbe2 - n vbe1 )/ln(n vr2 /n vr1 ) four-current method: t = 0.1771 x v ref ((n vbe2 + n vbe3 - n vbe1 - n vbe4 )/ln(n vr2 xn vr3 /n vr1 /n vr4 ) the natural log function (ln) is eliminated from the cal- culation by using an approximation. due to the small part-to-part variation in current ratios, this approxima- tion is extremely accurate. two-current method without an ln function: t = 0.1771 x v ref (n vbe2 ?n vbe1 )/(2.7081 + 2_(n vr2 /n vr1 - 15)/(n vr2 /n vr1 + 15) four-current method without an ln function: t = 0.1771 x v ref (n vbe2 + n vbe3 - n vbe1 - n vbe4 )/(2.0794 + 2(n vr2 x n vr3 /n vr1 /n vr4 - 8)/ (n vr2 x n vr3 /n vr1 /n vr4 + 8) q = electron charge = 1.60219 x 10 -19 coulombs n = diode ideality = 1.000 (typ) k = boltzmann's constant = 1.3807 x 10 -23 joules/kelvin i1 = nominal current (4?) i2 = nominal current ng (60?) i3 = nominal current (64?) i4 = nominal current (120?) to convert the measured temperature in kelvin to degrees celsius, the following formula is used: ? = k - 273.15 for the external temperature measurement, a transistor such as the 2n3904 is recommended. voltage reference and buffer an internal 1.25v bandgap reference has a buffer with a selectable 1.0v/v, 1.638v/v, or 2.0v/v gain, result- ing in nominally 1.25v, 2.048v, or 2.5v reference volt- age at ref. the adc and dacs use this reference voltage. the state of the internal voltage reference output buffer at por is disabled so it can be driven, at ref, with an external reference between agnd and av dd . the MAX1358B reference has an initial toler- ance of ?%. program the reference buffer through the serial interface. bypass ref with a 4.7? capaci- tor to agnd. uncommitted operational amplifiers (op amps) the MAX1358B includes one op amp. the op amp fea- tures rail-to-rail outputs, near rail-to-rail inputs, and has an 80khz (1nf load) input bandwidth. the daca_op (dacb_op) register controls the power state of the op amps. when powered down, the outputs of the op amps is high impedance. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 34 ______________________________________________________________________________________ single-pole/double-throw (spdt) switches the MAX1358B provides two uncommitted spdt switch- es. each switch has a typical 35 ? on-resistance. control the switches through the sw_ctrl register, the pwm output, and/or a upio port configured to control the switches (upio1?pio4_ctrl register). pulse-width modulator (pwm) a single 8-bit pwm is available for various system tasks such as lcd bias control, sensor bias voltage trim, buzzer drive, and duty-cycled sleep-mode power-con- trol schemes. pwm input clock sources include the 4.9512mhz fll output, the 32khz clock, and frequen- cy-divided versions of each. although most ?s have built-in pwm functions, the MAX1358B pwm is more flexible by allowing the upio outputs to be driven to dv dd or regulated cpout logic-high voltage levels. for duty-cycled power-control schemes, use the 32khz-derived input clock. the pwm output is avail- able independent of ? power state. the fll is typical- ly disabled in sleep-override mode. serial interface the MAX1358B features a 4-wire serial interface con- sisting of a chip select ( cs ), serial clock (sclk), data in (din), and data out (dout). cs must be low to allow data to be clocked into or out of the device. dout is high impedance while cs is high. the data is clocked in at din on the rising edge of sclk. data is clocked out at dout on the falling edge of sclk. the serial interface is compatible with spi modes cpol = 0, cpha = 0 and cpol = 1, cpha = 1. a write operation to the MAX1358B takes effect on the last rising edge of sclk. if cs goes high before the complete transfer, the write is ignored. every data transfer is initiated by the command byte. the command byte consists of a start bit (msb), r/ w bit, and 6 address bits. the start bit must be 1 to perform data transfers to the device. zeros clocked in are ignored. for spi pass-through mode, see the upio_spi register section. an address byte identifies each register. table 4 shows the com- plete register address map for this family of das. figures 14, 15, and 16 provide timing diagrams for read and write commands. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 35 cs sclk din dout x = don?t care. 1 0 a5 a4 a3 a2 a1 a0 d n d n -1 d n-2 d n-3 d 2 d 1 d 0 x x figure 14. serial-interface register write with 8-bit control word, followed by a variable length data write cs sclk din dout 1 1 a5 a4 a3 a2 a1 a0 x x x x x x x x x d n d n-1 d n-2 d n-3 d 2 d 1 d 0 x = don?t care. figure 15. serial-interface register read with 8-bit control word, followed by a variable length data read cs sclk din dout 1 0 a4 a3 a2 a1 drdy d0 a0 d7 d6 d5 d4 d3 d2 d1 x d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 1 1 a4 a3 a2 a1 a0 x adc conv changes x = don?t care. figure 16. performing an adc conversion ( drdy function can be accessed at upio pins) datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 36 ______________________________________________________________________________________ register name start ctl (r/ w ) adr<5:0> (address) d<39:0>, d<23:0>, d<15:0> or d<7:0> (data) adce strt bip pol cont adcref gain<1:0> adc 1 r/ w 0 0 0 0 0 x rate<2:0> mode<2:0> x x mux 1 r/ w 0 0 0 0 1 s muxp<3:0> muxn<3:0> data 1 r 0 0 0 1 0 x adc<15:0> offset cal 1 r/ w 0 0 0 1 1 x offset<23:0> gain cal 1 r/ w 0 0 1 0 0 x gain<23:0> reserved 1 r/ w 0 0 1 0 1 x reserved. do not use. dae dbe op1e x x x daca<9:8> daca_op 1 r/ w 0 0 1 1 0 x daca<7:0> dae dbe op1e x x x dacb<9:8> dacb_op 1 r/ w 0 0 1 1 1 x dacb<7:0> ref_sdc 1 r/ w 0 1 0 0 0 x refv<1:0> aoff aon sdce tsel<2:0> asec<19:4> al_day 1 r/ w 0 1 0 0 1 x asec<3:0> x x x x reserved 1 r/ w 0 1 0 1 0 x reserved. do not use. awe ade x rwe rtce osce flle hfce clk_ctrl 1 r/ w 0 1 0 1 1 x cksel<2:0> io32e ck32e clke intp wde sec<31:0> rtc 1 r/ w 0 1 1 0 0 x sub<7:0> pwme fsel<2:0> swah swal swbh swbl pwm_ctrl 1 r/ w 0 1 1 0 1 x spd1 spd2 x x x x x x pwmth<7:0> pwm_thtp 1 r/ w 0 1 1 1 0 x pwmtp<7:0> watchdog 1 w 0 1 1 1 1 x x x x x x x x x norm_md 1 w 1 0 0 0 0 x x x x x x x x x sleep 1 w 1 0 0 0 1 x x x x x x x x x sleep_cfg 1 r/ w 1 0 0 1 0 slp sosce sck32e spwme shdn x x x x upio4_ctrl 1 r/ w 1 0 0 1 1 x up4md<3:0> pup4 sv4 alh4 ll4 upio3_ctrl 1 r/ w 1 0 1 0 0 x up3md<3:0> pup3 sv3 alh3 ll3 upio2_ctrl 1 r/ w 1 0 1 0 1 x up2md<3:0> pup2 sv2 alh2 ll2 upio1_ctrl 1 r/ w 1 0 1 1 0 x up1md<3:0> pup1 sv1 alh1 ll1 upio_spi 1 r/ w 1 0 1 1 1 x up4s up3s up2s up1s x x x x sw_ctrl 1 r/ w 1 1 0 0 0 x swa swb spdt1<1:0> spdt2<1:0> x x temp_ctrl 1 r/ w 1 1 0 0 1 x imux<1:0> ival<1:0> x x x x reserved 1 r 1 1 0 1 0 x reserved. do not use. mldvd mlcpd mado msdc mcrdy madd mald x imsk 1 r/ w 1 1 0 1 1 x mupr<4:1> mupf<4:1> reserved 1 r/ w 1 1 1 0 0 x reserved. do not use. ps_vmons 1 r/ w 1 1 1 0 1 x ldoe cpe lsde cpde hyse rste x x reserved 1 r/ w 1 1 1 1 0 x reserved. do not use. ldvd lcpd adou sdc crdy add ald x status 1 r 1 1 1 1 1 x upr<4:1> upf<4:1> register definitions table 4. register address map x = don? care. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 37 the adc register configures the adc and starts a conversion. adce: adc power-enable bit. adce = 1 powers up the adc, and adce = 0 powers down the adc. strt: adc start bit. strt = 1 resets the registers inside the adc filter and initiates a conversion or cali- bration. the conversion begins immediately after the 16th adc control bit is clocked by the rising edge of sclk. the initial conversion requires four conversion cycles for valid output data. if cont = 0 when strt is asserted, the adc stops after a single conversion and holds the result in the data register. if cont = 1 when strt is asserted, the adc performs continuous conver- sions at the rate specified by the rate<2:0> bits until cont is deasserted or adce is deasserted, powering down the adc. the strt bit is automatically deasserted after the initial conversion is complete (four conversion cycles; the adc status bit add in the status register asserts). the current adc configurations are not affect- ed if the adc register is written with strt = 0. this allows the adc and mux configurations to be updated simultaneously with the s bit in the mux register. bip: unipolar/bipolar bit. set bip = 0 for unipolar mode and bip = 1 for bipolar mode. unipolar-mode data is unsigned binary format and bipolar is two? complement. see the adc transfer functions section for more details. pol: polarity flipper bit. pol = 1 flips the polarity of the differential signal to the adc and the input to the signal- detect comparator (sdc). pol = 0 sets the positive mux output to the positive adc and sdc inputs, and the neg- ative mux output to the negative adc and sdc inputs. pol = 1 sets the positive mux output to the negative adc and sdc inputs, and the negative mux output to the positive adc and sdc inputs. cont: continuous conversion bit. cont = 1 enables continuous conversions following completion of the first conversion or calibration(s) initiated by the strt or s bit. set cont = 0 while asserting the strt bit, or prior to asserting the s bit to perform a single conversion or to prevent conversions following a calibration. set cont = 0 to abort continuous conversions already in progress. when the adc is stopped in this way, the last complete conversion result remains in the data register and the internal adc state information is lost. asserting the cont bit does not restart the adc, but results in continuous conversions once the adc is restarted with the strt or s bit. adcref: adc reference source bit. set adcref = 0 to select ref as the adc reference. set adcref = 1 to select av dd as the adc reference. to measure the av dd voltage without having to attenuate the supply voltage, select ref and agnd as the differential inputs to the adc, with pol = 0 and while adcref = 1. gain<1:0>: adc gain-setting bits. these two bits select the gain of the adc as shown in table 5. msb lsb adce strt bip pol cont adcref gain<1:0> rate<2:0> mode<2:0> x x adc register (power-on state: 0000 0000 0000 00xx) register bit descriptions gain setting (v/v) gain1 gain0 100 201 410 811 table 5. setting the gain of the adc datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 38 ______________________________________________________________________________________ rate<2:0>: adc conversion-rate-setting bits. these three bits set the conversion rate of the adc as shown in table 6. the initial conversion requires four conver- sion cycles for valid data, and subsequent conversions require only one cycle (if cont = 1). a full-scale input change can require up to five cycles for valid data if the digital filter is not reset with the strt or s bit. mode<2:0>: conversion-mode bits. these three bits determine the type of conversion for the adc as shown in table 7. when the adc finishes an offset calibration and/or gain calibration, the mode<2:0> bits clear to 0 hex, the add bit in the status register asserts, and an interrupt asserts on int (or upio_ if programmed as drdy) if madd is unmasked. perform a gain calibra- tion after achieving the desired offset (calibrated or not). if an offset and gain calibration are performed together (mode<2:0> = 7 hex), the offset calibration is performed first followed by the gain calibration, and the ? is interrupted by int (or upio_ if programmed as drdy) if madd is unmasked only upon completion of both offset and gain calibration. after power-on or cali- bration, the adc does not begin conversions until initi- ated by the user (see the adce and strt bit descriptions in this section and see the s bit descrip- tions in the mux register section). see the gain cal register and offset cal register sections for details on system calibration. conversion mode mode2 mode1 mode0 normal 0 0 0 system offset calibration 0 0 1 system gain calibration 0 1 0 normal 0 1 1 normal 1 0 0 self-offset calibration 1 0 1 self-gain calibration 1 1 0 self-offset and gain calibration 1 1 1 table 7. setting the adc conversion mode nominal continuous conversion rate (sps) decimation ratio actual continuous conversion rate (sps) 10 1096 10.01 40 274 40.04 50 220 49.87 60 183 59.95 200 55 199.48 240 46 238.51 400 27 406.35 477 23 477.02 continuous conversion rate (sps) single conversion rate (sps) rate2 rate1 rate0 10 2.5 0 0 0 40 10 0 0 1 50 12.5 0 1 0 60 15 0 1 1 200 50 1 0 0 240 60 1 0 1 400 100 1 1 0 477 128 1 1 1 table 6a. setting the adc conversion rate* *calculate the adc sampling rate using the following equation: where f hfclk = 4.9152mhz nominally. f f decimation ratio s hfclk = 448 table 6b. actual adc conversion rates datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 39 the mux register configures the positive and negative mux inputs and can start an adc conversion. s (adr0): conversion start bit. the s bit is the lsb of the mux register address byte. s = 1 resets the regis- ters inside the adc filter and initiates a conversion or calibration. the conversion begins immediately after the eighth mux register data bit, when s = 1 and when writing to the mux register. this allows the new mux and adc register settings to take effect simultaneously for a new conversion, if strt = 0 during the last write to the adc register. if the s bit is asserted and the command is a read from the mux register, the conver- sion starts immediately after the s bit (adr0) is clocked in by the rising edge of sclk. read the mux register with s = 1 for the fastest method of initiating a conversion because only 8 bits are required. the subsequent mux register read is valid, but can be aborted by raising cs with no harmful side effects. the initial conversion requires four conversion cycles for valid output data. if cont = 0 and s = 1, the adc stops after a single conversion and holds the result in the data register. if cont = 1 and s = 1, the adc performs continuous conversions at the rate specified by the rate<2:0> bits until cont deasserts or adce deasserts, powering down the adc. when a conversion initiates using the s bit, the strt bit asserts and deasserts automatically after the initial conversion completes. writing to the mux register with s = 0 caus- es the mux settings to change immediately and the adc continues in its prior state with its settings unaf- fected. when the adc is powered down, mux inputs are open. muxp<3:0>: mux positive input bits. these four bits select one of 10 inputs from the positive mux to go to the positive output of the mux as shown in table 8. any writes to the mux register take effect immediately once the lsb (muxn0) is clocked by the rising edge of sclk. muxn<3:0> mux negative input bits. these four bits select one of 10 inputs from the negative mux to go to the negative output of the mux as shown in table 9. any writes to the mux register take effect immediately once the lsb (muxn0) is clocked by the rising edge of sclk. the data register contains the data from the most recently completed conversion. the offset cal register contains the 24-bit data of the most recently completed offset calibration. msb lsb s (adr0) muxp3 muxp2 muxp1 muxp0 muxn3 muxn2 muxn1 muxn0 mux register (power-on state: 0000 0000) positive mux input muxp3 muxp2 muxp1 muxp0 ain1 0000 sno1 0001 fba 0010 scm1 0011 fbb 0100 snc1 0101 in1- 0110 temp+0111 ref 1000 agnd 1001 101x open 11xx table 8. selecting the positive mux inputs x = don? care. negative mux input muxn3 muxn2 muxn1 muxn0 temp- 0 0 0 0 sno2 0 0 0 1 outa 0 0 1 0 scm2 0 0 1 1 outb 0 1 0 0 snc2 0 1 0 1 out1 0 1 1 0 ain2 0 1 1 1 ref 1 0 0 0 agnd 1 0 0 1 101x open 11xx table 9. selecting the negative mux inputs x = don? care. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 40 ______________________________________________________________________________________ offset<23:0>: offset-calibration bits. the data format is two? complement and is subtracted from the adc output before being written to the data register. the offset calibration allows input offset errors between v ref ?0% to be corrected in unipolar or bipolar mode. the MAX1358B can perform system offset calibration or self-offset calibration. self-calibration performs a cal- ibration for the entire signal path. see the adc calibration section for more details. the adc input voltage range specifications must always be obeyed, and the offset cal register effec- tively offsets the adc digital scale to a ?ero?value determined by the calibration. msb adc15 adc14 adc13 adc12 adc11 adc10 adc9 adc8 lsb adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 data register (power-on state: 0000 0000 0000 0000) adc<15:0> analog-to-digital conversion data bits. these 16 bits are the results from the most recently completed conversion. the data format is unsigned, binary for unipolar mode, and two? complement for bipolar mode. msb offset23 offset22 offset21 offset20 offset19 offset18 offset17 offset16 offset15 offset14 offset13 offset12 offset11 offset10 offset9 offset8 lsb offset7 offset6 offset5 offset4 offset3 offset2 offset1 offset0 offset cal register (power-on state: 0000 0000 0000 0000 0000 0000) msb gain23 gain22 gain21 gain20 gain19 gain18 gain17 gain16 gain15 gain14 gain13 gain12 gain11 gain10 gain9 gain8 lsb gain7 gain6 gain5 gain4 gain3 gain2 gain1 gain0 gain cal register (power-on state: 1000 0000 0000 0000 0000 0000) gain<23:0>: gain-calibration bits. the data format is unsigned binary with 23 bits to the right of the decimal point and scales the adc output before being written to the data register. the gain calibration allows full-scale errors between -v ref /2 and +v ref /2 to be corrected in unipolar mode and full-scale errors between (+50% x v ref ) and (+200% x v ref ) in unipolar or bipolar mode. the MAX1358B can perform system gain calibration or self-gain calibration. self-calibration performs a calibra- tion for offsets in the adc, and system calibration per- forms a calibration for the entire signal path. see the adc calibration section for more details. the adc input voltage range specifications must always be obeyed, and the gain cal register effectively scales the adc digital output to a full-scale value determined by the calibration. the usable gain-calibration range is limited to less than the full gain cal register digital- scaling range by the internal noise of the adc. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 41 writing to the daca_op output register updates daca on the rising sclk edge of the lsb data bit. the output voltage can be calculated as follows: v outa = v ref x n/2 10 where v ref is the reference voltage for the dac, and n is the integer value of the daca<9:0> output register. the output buffer is in unity gain. the daca data is 10 bits long and right justified. dae: daca enable bit. set dae = 1 to power up the daca and the daca output buffer in the MAX1358B. dbe: dacb enable bit. set dbe = 1 to power up the dacb and the dacb output buffer in the MAX1358B. this bit is mirrored in the dacb_op register. op1e: op1 power-enable bit. set op1e = 1 to power up op1 in the MAX1358B. this bit is mirrored in the dacb_op register. daca<9:0>: daca data bits. msb dae dbe op1e x x x daca9 daca8 lsb daca7 daca6 daca5 daca4 daca3 daca2 daca1 daca0 writing to the dacb_op output register updates dacb on the rising sclk edge of the lsb. the output voltage can be calculated as follows: v outb = v ref x n/2 10 where v ref is the reference voltage for the dac, and n is the integer value of dacb<9:0> output register. the output buffer is in unity gain. the dacb data is 10 bits long and right justified. dae: daca enable bit. set dae = 1 to power up daca and the daca output buffer in the MAX1358B. this bit is mirrored in the daca_op register. dbe: dacb enable bit. set dbe = 1 to power up dacb and the dacb output buffer in the MAX1358B. this bit is mirrored in the daca_op register. op1e: op1 power-enable bit. set op1e = 1 to power up op1 in the MAX1358B. this bit is mirrored in the daca_op register. dacb<9:0>: dacb data bits. daca_op register (power-on state: 000x xx00 0000 0000) msb dae dbe op1e x x x x x lsb xxxxxxxx dacb_op register (power-on state: 000x xx00 0000 0000) datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 42 ______________________________________________________________________________________ nominal threshold (mv) tsel2 tsel1 tsel0 00xx 50 100 100 1 0 1 150 1 1 0 200 1 1 1 table 11. setting the signal-detect comparator threshold x = don? care. the ref_sdc register contains bits to control the refer- ence voltage and signal-detect comparator. refv<1:0>: reference buffer voltage gain and enable bits. enables the output buffer, and sets the gain and the voltage at the ref pin as shown in table 10. power- on state is off to enable an external reference to drive the ref pin without contention. aoff: adc and dac/op-amp power-off bit. this bit pro- vides a method for turning off several analog functions with a single write. setting aoff = 1 deasserts the adce in the adc register and the dae, dbe, and op1e bits in the daca_op and dacb_op registers, powering down these analog blocks. setting aoff = 0 has no effect. the aon bit has priority when both aon and aoff bits are asserted. most of the analog functions can be disabled with a single write to the ref_sdc register by using aoff, refv<1:0>, and sdce. aon: adc and dac/op-amp power-on bit. this bit pro- vides a method of turning on several analog functions with a single write. setting aon = 1 asserts the adce bit in the adc register and dae, dbe, and op1e bits in the daca_op and dacb_op register, powering up these blocks. setting aon = 0 has no effect. the aon bit has priority when both aon and aoff bits are asserted. most of the analog functions can be enabled with a sin- gle write to the ref_sdc register using aon, refv<1:0>, and sdce. sdce: signal-detect comparator power-enable bit. set sdce = 1 to power up the signal-detect comparator, and set sdce = 0 to power down the signal-detect comparator. the adce bit in the adc register must be set to 1 to use the signal-detect comparator. tsel<2:0>: threshold-select bits. these bits select the threshold for the signal-detect comparator as shown in table 11. msb lsb refv1 refv0 aoff aon sdce tsel2 tsel1 tsel0 ref_sdc register (power-on state: 0000 0000) reference buffer gain (v/v) ref output voltage (v) refv1 refv0 disabled off (high impedance at ref) 00 1.0 1.25 0 1 1.638 2.048 1 0 2.0 2.5 1 1 table 10. setting the reference output voltage datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 43 msb asec19 asec18 asec17 asec16 asec15 asec14 asec13 asec12 asec11 asec10 asec9 asec8 asec7 asec6 asec5 asec4 lsb asec3 asec2 asec1 asec0 x x x x al_day register (power-on state: 0000 0000 0000 0000 0000 xxxx) the al_day register stores the second information of the time-of-day alarm. asec<19:0>: alarm-second bits. these 20 bits store the time-of-day alarm, which corresponds to the lower 20 bits of the rtc second counter or sec<19:0>. program the time-of-day alarm trigger between 1s to just over 12 days beyond the current rtc second counter value in increments of 1s. assert the awe bit in the clk_ctrl register (see the clk_ctrl register section) to enable writing to the al_day register. enabling the time-of-day alarm requires two writes to the clk_ctrl register. write the 20 alarm- second bits in 3 bytes, msb first. if cs is raised before the lsb is written, the alarm write is aborted, and the existing value remains. when the lower 20 bits in the rtc second counter match the contents of this register, the alarm triggers and asserts ald in the status register. it also asserts an interrupt on the int pin unless masked by the mald bit in the imsk register. the part enters normal mode if an alarm triggers while in sleep mode. the time- of-day alarm is intended to trigger single events. therefore, once it triggers, in the clk_ctrl register, the ade bit is automatically cleared, disabling the time-of- day alarm. implement a recurring alarm with repeated software writes over the serial interface each time the time-of-day alarm triggers. the time-of-day alarm can also be programmed to output at the upio pins. when configured this way the mald bit does not mask the upio alarm output. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 44 ______________________________________________________________________________________ msb awe ade x rwe rtce osce flle hfce lsb cksel2 cksel1 cksel0 io32e ck32e clke intp wde clk_ctrl register (power-on state: 00x0 1111 0010 1110) the clk_ctr register contains the control bits for the rtc alarms and clocks. awe: alarm write-enable bit. set awe = 1 to write data to the al_day register as well as the ade bit in this register. when awe = 0, all writes are prevented to the al_day register and the ade bit in this register. a sec- ond write to this register is required to change the value of the ade bit. the power-on default state is 0. ade: alarm (time-of-day) enable bit. set ade = 1 to enable the time-of-day alarm, and set ade = 0 to dis- able the time-of-day alarm. when enabled, the ald bit in the status register asserts when the rtc second counter time matches al_day register. the device wakes up from sleep to normal mode if not already awake. the ade bit can only be written if the awe = 1 from a previous write. the power-on default state is 0. rwe: rtc write-enable bit. set rwe = 1 prior to writing to the rtc register and the rtce bit in this register. if rwe = 0, all writes are prevented to the rtc register as well as the rtce bit in this register. the rwe signal takes effect after the rising edge of the 16th clock; therefore, a second write to this register is required to change the value of the rtce bit. the power-on default state is 0. rtce: real-time-clock enable bit. set rtce = 1 to enable the rtc, and set rtce = 0 to disable the rtc. the rtc has a 32-bit second and an 8-bit subsecond counter. the power-on default state is 1. osce: 32khz crystal-oscillator enable bit. set osce = 1 to power up the 32khz oscillator, and set osce = 0 to power down the oscillator. the power-on default state is 1. flle: frequency-locked-loop enable bit. set flle = 1 to enable the fll, and set flle = 0 to disable the fll. if hfce = 1 and flle = 0, the internal high-frequency oscillator is enabled, but it is not frequency-locked to the 32khz clock. when flle is asserted, it typically takes 3.5ms for the high-frequency clock to settle to within 1% of the 32khz reference clock frequency. switching the fll on or off with this bit does not cause high-frequency clock glitching. the power-on default state is 1. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 45 clk32k clk32k io32e 32kin, 32kout rtc, pwm, wdt clock source fll, c/p, sdc input source adc clock source output 1 0 xtal attached xtal xtal fll/hfclk input 0 1 xtal attached xtal clk32k fll/hfclk table 13. configuring the clk32k as an input or output hfce: high-frequency-clock enable bit. set hfce = 1 to enable the internal high-frequency clock source, and set hfce = 0 to disable the high-frequency clock source. if hfce = 1 and clke = 1, the internal high-frequency oscillator is enabled and is present at clk. the power- on default state is 1. cksel<2:0>: clock selection bits. these bits select the fll-based output clock frequency at the high-fre- quency clk pin as shown in table 12. the power-on default state is 001. io32e: input/output 32khz clock select bit. set io32e = 0 to configure the clk32k pin as an output, and set io32e = 1 to configure the clk32k pin as an input, regardless of the signal on the 32kin pin as shown in table 13. external clock frequencies applied to clk32k are clock sources to the fll, charge pump, and the signal- detect comparator. the default power-on state is 0. ck32e: clk32k output-buffer enable bit. set ck32e = 1 to enable the clk32k output buffer as long as osce = 1 and io32e = 0; otherwise, the ck32e bit is not asserted. set ck32e = 0 to disable the clk32k output buffer. the power-on default state is 1. clke: clk output-buffer enable bit. set clke = 1 to enable the clk output buffer. set clke = 0 to disable the buffer. disabling the buffer is useful for saving power in cases where the high-frequency clock is used internally but is not needed externally. if hfce = 0, or if clke = 0, clk remains low. the power-on default state is 1. intp: interrupt pin polarity bit. set intp = 1 to make int an active-high output when asserted, and set intp = 0 to make int an active-low output when asserted. the power-on default state is 1. wde: watchdog-enable bit. set wde = 1 to enable the watchdog timer, which asserts reset low within 500ms if the watchdog register is not written. set wde = 0 to disable the watchdog timer. the power-on default state is 0. clock frequency (khz) cksel2 cksel1 cksel0 4915.2 0 0 0 2457.6 0 0 1 1228.8 0 1 0 614.4 0 1 1 32.768 1 0 0 16.384 1 0 1 8.192 1 1 0 4.096 1 1 1 table 12. setting the clk frequency datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 46 ______________________________________________________________________________________ msb sec31 sec30 sec29 sec28 sec27 sec26 sec25 sec24 sec23 sec22 sec21 sec20 sec19 sec18 sec17 sec16 sec15 sec14 sec13 sec12 sec11 sec10 sec9 sec8 sec7 sec6 sec5 sec4 sec3 sec2 sec1 sec0 lsb sub7 sub6 sub5 sub4 sub3 sub2 sub1 sub0 rtc register (power-on state: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000) the rtc register stores the 40-bit second and subsec- ond count of the respective time-of-day and system clocks. sec<31:0>: the second bits store the time-of-day clock settings. it is a 32-bit binary counter with 1s reso- lution that can keep time for a span of over 136 years. firmware in the ? can translate this time count to units that are meaningful to the system (i.e., translate to cal- endar time or as an elapsed time from some predefined time = 0, such as january 1, 2000). the rtc runs con- tinuously as long as rtce = 1 (see the clk_cntl register section) and does not stop for reads or writes. the counter increments when the subsecond counter overflows. set rwe = 1 to enable writing to the rtc register. after writing to rwe, perform another write and set rtce = 1 to enable the rtc. a 40-bit burst write operation, starting with sec31 and finishing with sub0 is required to set the rtc second and subsec- ond bits. if cs is brought high before the 40th rising sclk edge, the write is aborted and the rtc contents are unchanged. the rtc register is loaded on the ris- ing sclk edge of the 40th bit (sub0). a 40-bit burst read operation, starting with sec31 and finishing with sub0, is required to retrieve the current rtc second and subsecond counts. the read command can be aborted prior to receiving the 40th bit (sub0) by raising cs and any rtc data read to that point is valid. when the read command is received, a snapshot of a valid rtc second count is latched to avoid reading an erro- neous, transitioning rtc value. due to the asynchro- nous nature of rtc reads, it is possible to have a maximum 1s error between the actual and reported times from the time-of-day clock. to prevent the data from changing during a read operation, complete reads of the rtc register in less than 1ms. the power-on default state is 0000 0000 hex. sub<7:0>: the subsecond bits store the system clock. this 8-bit binary counter has 3.9ms resolution (1/256hz) and a span of 1s. the subsecond counter increments in single counts from 00 hex to ff hex before rolling over again to 00 hex, at which time the rtc second counter (sec<31:0>) increments. the rtc runs continuously (as long as rtce = 1) and does not stop for reads or writes. a 256hz clock, derived from the 32khz crystal, increments this counter. set the rwe = 1 bit to enable writing to the rtc register. after writing to rwe, perform another write, setting rtce = 1, to enable the rtc. a 40-bit burst write operation, starting with sec31 and fin- ishing with sub0, is required to set the rtc second and subsecond bits. if cs is brought high before the 40th rising sclk edge, the write is aborted and the rtc con- tents are unchanged. the rtc register is loaded on the rising sclk edge of the 40th bit (sub0). a 40-bit burst read operation, starting with sec31 and finishing with sub0, is required to retrieve the current rtc second and subsecond counts. the read command can be aborted prior to receiving the 40th bit (sub0) by raising cs, and any rtc data read to that point is valid. when the read command is received, a snapshot of a valid rtc second count is latched to avoid reading an erro- neous, transitioning rtc value. due to the asynchro- nous nature of rtc reads, it is possible to have a maximum 1s error between the actual and reported times from the time-of-day clock. to prevent the data from changing during a read operation, complete reads of the rtc registers occur in less than 1ms. the power- on default state is 00 hex. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 47 msb pwme fsel2 fsel1 fsel0 swah swal swbh swbl lsb spd1 spd2 x x x x x x pwm_ctrl register (power-on state: 0000 0000 00xx xxxx) the pwm_ctrl register contains control bits for the 8-bit pwm. pwme: pwm-enable bit. set pwme = 1 to enable the internal pwm, and set pwme = 0 to disable the internal pwm. enable the high-frequency clock before enabling the pwm when using input clock frequencies above 32.768khz. the power-on default state is 0. fsel<2:0>: frequency selection bits. selects the pwm input clock frequency as shown in table 14. the power-on default is 000. swah: swa-switch pwm-high control bit. set swah = 1 to enable the pwm output to directly control the swa switch. when swah = swal, the pwm output is dis- abled from controlling the swa switch. when swah = 1, a pwm high output closes the swa switch and a pwm low output opens the swa switch. the pwm high output refers to the beginning of the period when the output is logic-high. see table 17 for more details. the power-on default is 0. swal: swa-switch pwm-low control bit. set swal = 1 to enable the inverted pwm output to directly control the swa switch. when swah = swal , the pwm output is disabled from controlling the swa switch. when swal = 1, a pwm low output closes the swa switch and a pwm high output opens the swa switch. the pwm low output refers to the end of the period when the output is logic-low. see table 17 for more details. the power-on default is 0. spd1: spdt1-switch pwm drive control bit. set spd1 = 1 to enable the pwm output to directly control the spdt1 switch, and set spd1 = 0 to disable the pwm output controlling the spdt1 switch. the spdt1<1:0> bits, the upio pins (if programmed), and the pwm out- put (if enabled), determine the spdt1-switch state. see table 18 for more details. the power-on default is 0. spd2: spdt2-switch pwm drive control bit. set spd2 = 1 to enable the pwm output to directly control the spdt2 switch, and set spd2 = 0 to disable the pwm output controlling the spdt2 switch. the spdt2<1:0> bits, the upio pins (if programmed), and the pwm out- put (if enabled), determine the spdt2-switch state. see table 19 for more details. the power-on default is 0. pwm input frequency* (khz) fsel2 fsel1 fsel0 4915.2** 0 0 0 2457.6** 0 0 1 1228.8** 0 1 0 32.768 0 1 1 8.192 1 0 0 1.024 1 0 1 0.256 1 1 0 0.032 1 1 1 table 14. setting the pwm frequency * the lower pwm frequencies are useful for power-supply duty cycling to conserve battery life and enable a single-battery cell- powered system. the higher frequencies allow reasonably small, external components for rc filtering when used as a dac for bias adjustments. ** when the part is in sleep mode, the hfclk is shut down. in this case, pwm frequencies above 32khz are not available (see spwme in the sleep_cfg register section). datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 48 ______________________________________________________________________________________ msb pwmth7 pwmth6 pwmth5 pwmth4 pwmth3 pwmth2 pwmth1 pwmth0 lsb pwmtp7 pwmtp6 pwmtp5 pwmtp4 pwmtp3 pwmtp2 pwmtp1 pwmtp0 pwm_thtp register (power-on state: 0000 0000 0000 0000) the pwm_thtp register contains the bits that set the pwm on-time and period. pwmth<7:0>: pwm time high bits. these bits define the pwm on (or high)-time and when combined with the pwmtp<7:0> bits, they determine the duty cycle and period. the on-time duty cycle is defined as: (pwmth<7:0> + 1)/(pwmtp<7:0> + 1) to get 50% duty cycle, set pwmth<7:0> to 126 deci- mal and pwmtp<7:0> to 253 decimal. note that setting pwmtp<7:0> to 255 decimal is not valid as the denom- inator in the above formula becomes 0. a 100% duty cycle (i.e., always on) is possible with a value of pwmth<7:0> pwmtp<7:0> > 0. a 0% duty cycle is possible by setting pwmth<7:0> = 0 or pwme = 0 in the pwm_ctrl register. if the pwm is selected to drive the upio_ pin(s), the alh_ bit(s) (upio_ctrl register) determine the on-time polarity at the beginning of the pwm cycle. if alh_ = 1, the on-time at the start of the pwm period causes a logic-high level (dv dd or cpout) at the upio_ pin. when alh_ = 0, it causes a logic-low level (dgnd) during the on-time. when the pwm output drives the swa/b switches, the swa(b)h or swa(b)l bits in the pwm_ctrl register determine which pwm phase closes these switches. the spdt1 and spdt2 switches do not have pwm polarity inver- sion bits (see the spdt1<1:0> and spdt2<1:0> bit descriptions in the sw_ctrl register section), but their effective polarity is set by how the switches are connected externally. the power-on default is 00 hex. pwmtp<7:0>: pwm time period bits. these bits con- trol the pwm output period defined. the pwm output period is defined as: (pwmtp<7:0> + 1)/(pwm input frequency) set the pwm input frequency by selecting the fsel<2:0> bits as described in table 14. the power- on default is 00 hex. watchdog register (power-on state: n/a) writing to the watchdog register address sets the watchdog timer to 0ms. if the watchdog is enabled (wde = 1) and the watchdog register is not written to before the 750ms expiration, reset asserts low for 250ms and the watchdog timer restarts at 0ms when the watchdog timer is enabled. there are no data bits for this register, and the watchdog timer is reset on the rising edge of sclk during the adr0 bit in the watchdog register address control byte. figure 17 shows an example of watchdog timing. norm_md register (power-on state: n/a) exit sleep mode and enter normal mode by writing to the norm_md register. the specific normal-mode state of all circuit blocks is set by the user, who must configure the individual power-enable bits before enter- ing sleep mode (table 15). there are no data bits for this register, and normal mode begins on the rising edge of sclk during the adr0 bit in the norm_md register address control byte. sleep register (power-on state: n/a) enter sleep mode by writing to the sleep register. this low-power state overrides most of the normal power- control bits. table 15 shows which functions are off, which functions are unaffected (ade, rtce, lsde, and hyse), and which functions are controlled by special sleep-mode bits (sosce, sck32e, and spwme) while in sleep mode. there are no data bits for this register, and sleep mode begins on the rising edge of sclk during the adr0 bit in the sleep register address con- trol byte. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 49 register name circuit block description por default normal mode sleep adc adc adce = 0 adce off daca dae = 0 dae off dacb dbe = 0 dbe off daca_op, dacb_op op1 op1e = 0 op1e off reference buffer gain and enable refv<1:0> = 00 refv<1:0> off ref_sdc signal-detect comparator sdce = 0 sdce off time-of-day alarm enable ade = 0 ade ade rtc rtce = 1 rtce rtce ck32 xtal oscillator osce = 1 osce sosce ck32 output buffer ck32e = 1 ck32e sck32e high-frequency clock hfce = 1 hfce off high-frequency clock output buffer clke = 1 clke off fll enable flle = 1 flle off clk_ctrl watchdog timer wde = 0 wde off pwm_ctrl pwm pwme = 0 pwme spwme linear regulator ldoe = 0 ldoe off charge-pump doubler cpe = 0 cpe off cpout voltage monitor cpde = 0 cpde off 1.8v dv dd monitor lsde = 1 lsde lsde ps_vmons 1.8v monitor hysteresis hyse = 0 hyse hyse temp_ctrl temperature sense source imux<1:0> = 00 imux<1:0> off upio_ function up_md<3:0> = 0 hex up_md<3:0> up_md<3:0> upio_ pullup pup_ = 1 pup_ pup_ upio_ supply voltage sv_ = 0 sv_ sv_ upio_ctrl upio_ assertion level alh_ = 0 alh_ alh_ table 15. normal-mode and sleep-register summary datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 50 ______________________________________________________________________________________ the sleep_cfg register allows users to program spe- cific behavior for the 32khz oscillator, buffer, and pwm in sleep mode. it also contains a sleep-control bit (slp) to enable sleep mode. slp (adr0): sleep bit. the slp bit is the lsb in the sleep_cfg address control byte. set slp = 1 to assert the shdn bit and enter sleep mode. writing the register with slp = 0 or reading with slp = 0 or slp = 1 has no effect on the shdn bit. sosce: sleep-mode 32khz crystal oscillator enable bit. sosce = 1 enables the 32khz oscillator in sleep mode, and sosce = 0 disables it in sleep mode, regardless of the state of the osce bit. the power-on default is 1. sck32e: sleep-mode ck32k-pin output-buffer enable bit. sck32e = 1 enables the 32khz output buffer in sleep mode, and sck32e = 0 disables it in sleep mode, regardless of the state of the ck32e bit. the power-on default is 1. spwme: sleep-mode pwm enable bit. spwme = 1 enables the internal pwm in sleep mode, and spwme = 0 disables it in sleep mode, regardless of the state of the pwme bit. input frequencies are limited to 32.768khz or lower since the high-frequency clock is disabled in sleep mode. sosce must be asserted to have 32khz avail- able as an input to the pwm. the power-on default is 0. shdn: shutdown bit. this bit is read only. shdn is asserted by writing to the sleep register address or by writing to the sleep_cfg register with slp = 1. when shdn is asserted, the device is in sleep mode even if the sleep or sleep function on the upio is deassert- ed. the shdn bit is deasserted by writing to the norm_md register or by other defined events. events that cause shdn to be deasserted are a day alarm or an edge on the upio wake-up pin causing wake-up to be asserted. the power-on default is 0. msb lsb slp (adr0) sosce sck32e spwme shdn x x x x sleep_cfg register (power-on state: 1100 xxxx) 4hz clock 2-bit counter x wde = 1 012 3 reset watchdog address 01 2 watchdog address watchdog address 01 0120 750ms 250ms spi writes d q q r ck dq q r ck divide- by-8192 32k wde por wdw watchdog timer 4hz reset figure 17. watchdog timer architecture datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 51 msb lsb up4md3 up4md2 up4md1 up4md0 pup4 sv4 alh4 ll4 upio4_ctrl register (power-on state: 0000 1000) msb lsb up3md3 up3md2 up3md1 up3md0 pup3 sv3 alh3 ll3 upio3_ctrl register (power-on state: 0000 1000) the upio4_ctrl register configures the upio4 pin functionality. up4md<3:0>: upio4-mode selection bits. these bits configure the mode for the upio4 pin. see table 16 for a detailed description. the power-on default is 0 hex. pup4: pullup upio4 control bit. set pup4 = 1 to enable a weak pullup resistor on the upio4 pin, and set pup4 = 0 to disable it. the pullup resistor is connected to either dv dd or cpout as programmed by the sv4 bit. the pullup is enabled only when upio4 is configured as an input. open-drain behavior can be simulated at upio4 by setting the mode to gpo with ll4 = 0 and by changing the mode to gpi with pup4 = 0, allowing external high pullup. the power-on default is 1. sv4: supply-voltage upio4 selection bit. set sv4 = 0 to select dv dd as the supply voltage for the upio4 pin, and set sv4 = 1 to select cpout as the supply volt- age. the selected supply voltage applies to all modes for the upio4 pin. the power-on default is 0. alh4: active logic-level assertion high upio4 bit. set alh4 = 0 to define the input or output assertion level for upio4 as low except when in gpi and gpo modes. set alh4 = 1 to define the input or output assertion level as high. for example, asserting alh4 defines the upio4 output signal as alarm, while deasserting alh4 defines it as alarm . similarly, asserting alh4 defines the upio4 input signal as wu, while deassert- ing alh4 defines it as wu . the power-on default is 0. ll4: logic-level upio4 bit. when upio4 is configured as gpo, ll4 = 0 sets the output to a logic-low and ll4 = 1 sets the output to a logic-high. a read of ll4 returns the voltage level at the upio4 pin at the time of the read, regardless of how it is programmed. the power-on default is 0. the upio3_ctrl register configures the upio3 pin functionality. up3md<3:0>: upio3-mode selection bits. these bits configure the mode for the upio3 pin. see table 16 for a detailed description. the power-on default is 0 hex. pup3: pullup upio3 control bit. set pup3 = 1 to enable a weak pullup resistor on the upio3 pin, and set pup3 = 0 to disable it. the pullup resistor is connected to either dv dd or cpout as programmed by the sv3 bit. the pullup is enabled only when upio3 is configured as an input. open-drain behavior can be simulated at upio3 by setting the mode to gpo with ll3 = 0 and by changing the mode to gpi with pup3 = 0, allowing external high pullup. the power-on default is 1. sv3: supply-voltage upio3 selection bit. set sv3 = 0 to select dv dd as the supply voltage for the upio3 pin, and set sv3 = 1 to select cpout as the supply volt- age. the selected supply voltage applies to all modes for the upio3 pin. the power-on default is 0. alh3: active logic-level assertion high upio3 bit. set alh3 = 0 to define the input or output assertion level for upio3 as low except when in gpi and gpo modes. set alh3 = 1 to define the input or output assertion level as high. for example, asserting alh3 defines the upio3 output signal as alarm, while deasserting alh3 defines it as alarm . similarly, asserting alh3 defines the upio3 input signal as wu, while deassert- ing alh3 defines it as wu . the power-on default is 0. ll3: logic-level upio3 bit. when upio3 is configured as gpo, ll3 = 0 sets the output to a logic-low and ll3 = 1 sets the output to a logic-high. a read of ll3 returns the voltage level at the upio3 pin at the time of the read, regardless of how it is programmed. the power-on default is 0. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 52 ______________________________________________________________________________________ msb lsb up2md3 up2md2 up2md1 up2md0 pup2 sv2 alh2 ll2 upio2_ctrl register (power-on state: 0000 1000) msb lsb up1md3 up1md2 up1md1 up1md0 pup1 sv1 alh1 ll1 upio1_ctrl register (power-on state: 0000 1000) the upio2_ctrl register configures the upio2 pin functionality. up2md<3:0>: upio2-mode selection bits. these bits configure the mode for the upio2 pin. see table 16 for a detailed description. the power-on default is 0 hex. pup2: pullup upio2 control bit. set pup2 = 1 to enable a weak pullup resistor on the upio2 pin, and set pup2 = 0 to disable it. the pullup resistor is connected to either dv dd or cpout as programmed by the sv2 bit. the pullup is enabled only when upio2 is configured as an input. open-drain behavior can be simulated at upio2 by setting the mode to gpo with ll2 = 0 and by changing the mode to gpi with pup2 = 0, allowing external high pullup. the power-on default is 1. sv2: supply-voltage upio2 selection bit. set sv2 = 0 to select dv dd as the supply voltage for the upio2 pin, and set sv2 = 1 to select cpout as the supply volt- age. the selected supply voltage applies to all modes for the upio2 pin. the power-on default is 0. alh2: active logic-level assertion high upio2 bit. set alh2 = 0 to define the input or output assertion level for upio2 as low except when in gpi and gpo modes. set alh2 = 1 to define the input or output assertion level as high. for example, asserting alh2 defines the upio2 output signal as alarm, while deasserting alh2 defines it as alarm . similarly, asserting alh2 defines the upio2 input signal as wu, while deassert- ing alh2 defines it as wu . the power-on default is 0. ll2: logic-level upio2 bit. when upio2 is configured as gpo, ll2 = 0 sets the output to a logic-low and ll2 = 1 sets the output to a logic-high. a read of ll2 returns the voltage level at the upio2 pin at the time of the read, regardless of how it is programmed. the power-on default is 0. the upio1_ctrl register configures the upio1 pin functionality. up1md<3:0>: upio1-mode selection bits. these bits configure the mode for the upio1 pin. see table 16 for a detailed description. the power-on default is 0 hex. pup1: pullup upio1 control bit. set pup1 = 1 to enable a weak pullup resistor on the upio1 pin, and set pup1 = 0 to disable it. the pullup resistor is connected to either dv dd or cpout as programmed by the sv1 bit. the pullup is enabled only when upio1 is configured as an input. open-drain behavior can be simulated at upio1 by setting the mode to gpo with ll1 = 0 and by changing the mode to gpi with pup1 = 0, allowing external high pullup. the power-on default is 1. sv1: supply-voltage upio1 selection bit. set sv1 = 0 to select dv dd as the supply voltage for the upio1 pin, and set sv1 = 1 to select cpout as the supply volt- age. the selected supply voltage applies to all modes for the upio1 pin. the power-on default is 0. alh1: active logic-level assertion high upio1 bit. set alh1 = 0 to define the input or output assertion level for upio1 as low except when in gpi and gpo modes. set alh1 = 1 to define the input or output assertion level as high. for example, asserting alh1 defines the upio1 output signal as alarm, while deasserting alh1 defines it as alarm . similarly, asserting alh1 defines the upio1 input signal as wu, while deassert- ing alh1 defines it as wu . the power-on default is 0. ll1: logic-level upio1 bit. when upio1 is configured as gpo, ll1 = 0 sets the output to a logic-low and ll1 = 1 sets the output to a logic-high. a read of ll1 returns the voltage level at the upio1 pin at the time of the read, regardless of how it is programmed. the power-on default is 0. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 53 up4md<3:0>, up3md<3:0>, up2md<3:0>, up1md<3:0> mode description 0 0 0 0 gpi general-purpose digital input. active edges detected by upr_ or upf_ status register bits. alh_ has no effect with this setting. 0 0 0 1 gpo general-purpose digital output. logic level set by ll_ bit. alh_ has no effect with this setting. 0 0 1 0 swa or swa digital input. dac a buffer switch control. see the swa bit description in the sw_ctrl register section. 0 0 1 1 swb or swb digital input. dac b buffer switch control. see the swb bit description in the sw_ctrl register section. 0 1 0 0 spdt1 or spdt1 digital input. spdt1 switch control. see the spdt1<1:0> bit description in the sw_ctrl register section. 0 1 0 1 spdt2 or spdt2 digital input. spdt2 switch control. see the spdt2<1:0> bit description in the sw_ctrl register section. 0 1 1 0 sleep or sleep sleep-mode digital input. overrides power-control register and puts the part into sleep mode when asserted. the clock buffers must be powered down separately. when deasserted, power mode is determined by the shdn bit. 0 1 1 1 wu or wu wake-up digital input. asserted edge clears shdn bit. 1 0 0 0 1 0 0 1 1 0 1 0 reserved reserved. do not use these settings. 1 0 1 1 pwm or pwm pwm digital output. signal defined by the pwm_ctrl register. pwm on (or high or 1); assertion level defined by the alh_ bit. when pwm is disabled (pwme = 0), the upio pin idles high (dv dd or cpout) if alh = 1, and low (dgnd) if alh = 0. 1 1 0 0 shdn or shdn power-supply shutdown digital output. equivalent to shdn bit. power-on default of gpi with pullup ensures initial power-supply turn-on when upio is connected to a power supply with a shdn input. 1 1 0 1 al_day or al_day rtc alarm digital output. asserts for time-of-day alarm events; equivalent to ald in status register. 1 1 1 0 reserved reserved. do not use these settings. 1 1 1 1 drdy or drdy adc data-ready digital output. asserts when analog-to-digital conversion or calibration completes. not masked by madd bit. table 16. upio mode configuration note: when multiple upio inputs are configured for the same input function, the inputs are ored together. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 54 ______________________________________________________________________________________ msb lsb up4s up3s up2s up1s x x x x upio_spi register (power-on state: 0000 xxxx) cs write to das to enable spi mode write through das to upio device normal write to das sclk din d n d n-1 d n-2 d n-3 d 3 d 2 d 1 d 0 e n e n-1 e n-2 e n-3 x x x x e n e n-1 e n-2 e n-3 x x x x d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 dout e 3 e 2 e 1 e 0 e 3 e 2 e 1 e 0 upio4 set by upio4_ctrl register set by upio4_ctrl register upio3 set by upio3_ctrl register set by upio3_ctrl register upio2 set by upio2_ctrl register set by upio2_ctrl register upio1 set by upio1_ctrl register set by upio1_ctrl register figure 18. spi pass-through timing diagram the upio_spi pass-through control register bits map the serial interface signals to the upio pins, allowing the das to drive other devices at cpout or dv dd volt- age levels, depending on the sv_ bit setting found in the upio_ctrl register. individual bits are provided to set only the desired upio inputs to the spi pass- through mode. this mode becomes active when cs is driven high to complete the write to this register, and remains active as long as cs stays high (i.e., multiple pass-through writes are possible). the spi pass- through mode is deactivated immediately when cs is pulled low for the next das write. the upio_ state (both before and after the spi pass- through mode) is set by the up_md<3:0> and ll_ bits. when a upio is configured for spi pass-through mode and the cs is high, upr_, upf_, and ll_ continue to detect upio_ edges, which can still generate interrupts. see figure 18 for an spi pass-through timing diagram. up4s: upio4 spi pass-through-mode enable bit. a logic 1 maps the inverted cs signal to the upio4 pin. therefore, upio4 is low (near dgnd) when spi pass- through mode is active, and is high (near dv dd or cpout) when the mode is inactive. a logic 0 disables the upio4 spi pass-through mode. the power-on default is 0. up3s: upio3 spi pass-through-mode enable bit. a logic 1 maps the sclk signal to upio3 (directly with no inversion), while a logic 0 disables the upio3 spi pass- through mode. the power-on default is 0. up2s: upio2 spi pass-through-mode enable bit. a logic 1 maps the din signal to upio2 (directly with no inversion), while a logic 0 disables the upio2 spi pass- through mode. the power-on default is 0. up1s: upio1 spi pass-through-mode enable bit. a logic 1 maps the upio1 input signal to dout (directly with no inversion), while a logic 0 disables the upio1 spi pass-through mode. the power-on default is 0. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 55 the switch-control register controls the two spdt switches (spdt1 and spdt2) and the daca output buffer spst switch (swa). control this switch by the serial bits in this register, by any of the upio pins that are enabled for that function, or by the pwm. swa: daca output buffer spst-switch a control bit. the swa bit, the upio inputs (if configured), and the pwm (if configured) control the state of the swa switch as shown in table 17. the upio_ states of 0 and 1 in the table correspond to respective deasserted and asserted logic states as defined by the alh_ bit of the upio_ctrl register. if a upio is not configured for this mode, its value applied to the table is 0. the pwm states of 0 and 1 in the table correspond to the respec- tive pwm off (or low) and on (or high) states defined by the swah and swal bits (see the pwm_ctrl register section). if the pwm is not configured for this mode, its value applied to the table is 0. the power-on default is 0. swb: dacb output buffer spst-switch b control bit. the swb bit, the upio inputs (if configured), and the pwm (if configured) control the state of the swb switch as shown in table 18. the upio_ states of 0 and 1 in the table correspond to respective deasserted and asserted logic states as defined by the alh_ bit (see the upio_ctrl register section). if a upio is not config- ured for this mode, its value applied to the table is 0. the pwm states of 0 and 1 in the table correspond to the respective pwm off (or low) and on (or high) states defined by the swbh and swbl bits (see the pwm_ctrl register section). if the pwm is not config- ured for this mode, its value applied to the table is 0. the power-on default is 0. spdt1<1:0>: single-pole double-throw switch 1 con- trol bits. the spdt1<1:0> bits, the upio pins (if config- ured), and the pwm (if configured) control the state of the switch as shown in table 18. the upio_ states of 0 and 1 in the table correspond to respective deasserted and asserted logic states as defined by the alh_ bit of the upio_ctrl register. if a upio is not configured for this mode, its value applied to table 18 is 0. the pwm states of 0 and 1 in table 18 correspond to the respec- tive pwm off (low) and on (high) states defined by the spd1 bit in the pwm_ctrl register. if the pwm is not configured for this mode, its value applied to table 18 is 0. the power-on default is 00. msb lsb swa swb spdt11 spdt10 spdt21 spdt20 x x sw_ctrl register (power-on state: 0000 00xx) sw_ bit* upio_* pwm* sw_ switch state 0 0 0 switch open x x 1 switch closed x 1 x switch closed 1 x x switch closed table 17. swa states x = don? care. * switch sw_ control is effectively an or of the sw_ bit, upio_ pins, and pwm. spdt1<1:0> upio_* pwm* spdt1 switch state 0 0 0 0 sno1 open, snc1 open 0 x x 1 sno1 closed, snc1 closed 0 x 1 x sno1 closed, snc1 closed 0 1 x x sno1 closed, snc1 closed 1 0 0 0 snc1 closed, sno1 open 1 x x 1 snc1 open, sno1 closed 1 x 1 x snc1 open, sno1 closed 1 1 x x snc1 open, sno1 closed table 18. spdt switch 1 states x = don? care. * switch spdt1 control is effectively an or of the spdt10 bit, the upio_ pins, and the pwm output. the spdt11 bit determines if the switches open and close together or if they toggle. spdt2<1:0> upio_* pwm* spdt2 switch state 0 0 0 0 sno2 open, snc2 open 0 x x 1 sno2 closed, snc2 closed 0 x 1 x sno2 closed, snc2 closed 0 1 x x sno2 closed, snc2 closed 1 0 0 0 snc2 closed, sno2 open 1 x x 1 snc2 open, sno2 closed 1 x 1 x snc2 open, sno2 closed 1 1 x x snc2 open, sno2 closed table 19. spdt switch 2 states x = don? care. * switch spdt2 control is effectively an or of the spdt20 bit, the upio_ pins, and the pwm output. the spdt21 bit determines if the switches open and close together or if they toggle. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 56 ______________________________________________________________________________________ the temperature-sensor control register controls the internal and external temperature measurement. imux<1:0>: internal current-source mux bits. selects the pin to be driven by the internal current sources as shown in table 20. the power-on default is 00. ival<1:0>: internal current-source value bits. selects the value of the internal current source as shown in table 21. the power-on default is 00. spdt2<1:0>: single-pole double-throw switch 2 control bits. the spdt2<1:0> bits, the upio pins (if config- ured), and the pwm (if configured) control the state of the switch as shown in table 19. the upio_ states of 0 and 1 in the table correspond to respective deasserted and asserted logic states as defined by the alh_ bit in the upio_ctrl register. if a upio is not configured for this mode, its value applied to table 19 is 0. the pwm states of 0 and 1 in table 19 correspond to the respec- tive pwm off (low) and on (high) states defined by the spd2 bit in the pwm_ctrl register. if the pwm is not configured for this mode, its value applied to table 19 is 0. the power-on default is 00. msb lsb imux1 imux0 ival1 ival0 x x x x temp_ctrl register (power-on state: 0000 xxxx) current source imux1 imux0 disabled 0 0 internal temperature sensor 0 1 ain1 1 0 ain2 1 1 table 20. selecting internal current source current typical current (?) ival1 ival0 i 1 400 i 2 60 0 1 i 3 64 1 0 i 4 120 1 1 table 21. setting the current level datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 57 msb mldvd mlcpd mado msdc mcrdy madd mald x lsb mupr4 mupr3 mupr2 mupr1 mupf4 mupf3 mupf2 mupf1 imsk register (power-on state: 1111 011x 1111 1111) msb lsb ldoe cpe lsde cpde hyse rste x x ps_vmons register (power-on state: 0010 01xx) this register is the power-supply and voltage monitors control register. ldoe: low-dropout linear-regulator enable bit. set ldoe = 1 to enable the low-dropout linear regulator to provide the internal source voltage for the charge pump. set ldoe = 0 to disable the ldo, allowing an external drive to the charge-pump input through reg. the power-on default value is 0. cpe: charge-pump enable bit. set cpe = 1 to enable the charge-pump doubler, and set cpe = 0 to disable the charge-pump doubler. the power-on default value is 0. lsde: dv dd low-supply voltage-detector power- enable bit. set lsde = 1 to enable the +1.8v (dv dd ) low-supply-voltage detector, and set lsde = 0 to disable the dv dd low-supply-voltage detector. the power-on default value is 1. cpde: cpout low-supply voltage-detector power- enable bit. set cpde = 1 to enable the +2.7v cpout low-supply voltage-detector comparator, and set cpde = 0 to disable the cpout low-supply voltage-detector comparator. the power-on default value is 0. hyse: dv dd low-supply voltage-detector hysteresis- enable bit. set hyse = 1 to set the hysteresis for the +1.8v (dv dd ) low-supply-voltage detector to +200mv, and set hyse = 0 to set the hysteresis to +20mv. on initial power-up, the hysteresis is +20mv and can be pro- grammed to 200mv once reset goes high. once pro- grammed to +200mv, the dv dd falling threshold is +1.8v nominally and the rising threshold is +2.0v nominally. the the imsk register determines which bits of the status register generate an interrupt on int. the bits in this register do not mask output signals routed to upio since the output signals are masked by disabling that upio function. mldvd: ldvd status bit mask. set mldvd = 0 to enable the ldvd status bit interrupt to int, and set mldvd = 1 to mask the ldvd status bit interrupt. the power-on default value is 1. mlcpd: lcp status bit mask. set mlcpd = 0 to enable the lcp status bit interrupt to int, and set mlcpd = 1 to mask the lcp status bit interrupt. the power-on default value is 1. mado: ado status bit mask. set mado = 0 to enable the ado status bit interrupt to int, and set mado = 1 to mask the ado status bit interrupt. the power-on default value is 1. msdc: sdc status bit mask. set msdc = 0 to enable the sdc status bit interrupt to int, and set msdc = 1 to mask the sdc status bit interrupt. the power-on default value is 1. mcrdy: crd status bit mask. set mcrdy = 0 to enable the crdy status bit interrupt to int, and set mcrdy = 1 to mask the crdy status bit interrupt. the power-on default value is 0. madd: add status bit mask. set madd = 0 to enable the add status bit interrupt to int, and set madd = 1 to mask the add status bit interrupt. the power-on default value is 1. mald: ald status bit mask. set mald = 0 to enable the ald status bit interrupt to int, and set mald = 1 to mask the ald status bit interrupt. the power-on default value is 1. mupr<4:1>: upr<4:1> status bits mask. set mupr_ = 0 to enable the upr_ status bit interrupt to int, and set mupr_ = 1 to mask the upr_ status bit interrupt. (_ = 1, 2, 3, or 4 and corresponds to the upio1, upio2, upio3, or upio4 pins, respectively.) the power-on default value is f hex. mupf<4:1>: upf<4:1> status bits mask. set mupf_ = 0 to enable the upf_ status bit interrupt to int, and set mupf_ = 1 to mask the upf_ status bit interrupt. (_ = 1, 2, 3, or 4 and corresponds to the upio1, upio2, upio3, or upio4 pins, respectively.) the power-on default value is f hex. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 58 ______________________________________________________________________________________ msb ldvd lcpd adou sdc crdy add ald x lsb upr4 upr3 upr2 upr1 upf4 upf3 upf2 upf1 status register (power-on state: 0000 000x 0000 0000) the status register contains the status bits of events in various system blocks. any status bits not masked in the imsk register cause an interrupt on int. some of the status bit setting events (gpi, wakeup, alarm, drdy) can be directed to upio_ to provide multiple ? inter- rupt inputs. there are no specific mask bits for the upio interrupt signals since the bits are effectively masked by selecting a different function for upio. the status bits always record the triggering event(s), even for masked bits, which do not generate an interrupt on int. it is pos- sible to set multiple status bits during a single int interrupt event. clear all status bits except for add and adou by reading the status register. during a status register read, int deasserts when the first status data bit (ldvd) reads out (9th rising sclk) and remains deasserted until shortly after the last status data bit (~15ns). at this point, int reasserts if any status bit is set during the status register read. if the status register is partially read (i.e., the read is aborted midway), none of the status bits are cleared. new events occurring during a status register read, or events that persist after reading the status bits result in another interrupt immediately after the status register read finishes. this is a read-only register. ldvd: low dv dd voltage-detector status bit. ldvd = 1 indicates dv dd is below the +1.8v threshold; otherwise ldvd = 0. ldvd clears during the status register read as long as the condition does not persist. otherwise, the ldvd bit reasserts immediately. if the dv dd low voltage detector is disabled, ldvd = 0. the power-on default is 0. lcpd: low cpout voltage-detector status bit. lcpd = 1 indicates cpout is below the +2.7v threshold; other- wise lcpd = 0. lcpd clears during the status regis- ter read as long as the condition does not persist. otherwise the lcpd bit reasserts immediately. lcpd = 0 when the cpout low voltage detector is disabled. the power-on default is 0. adou: adc overflow/underflow status bit. adou = 1 indicates an adc underflow or overflow condition in the current adc result. new conversions that are valid clear the adou bit. adou = 0 when the adc data is valid or the adc is disabled (adce = 0). an underflow condition occurs when the adc data is theoretically less than 0000 hex in unipolar mode and less than 8000 hex in bipolar mode. an overflow condition occurs when the adc data is theoretically greater than ffff hex in unipolar mode and greater than 7fff hex in bipolar mode. use this bit to determine the validity of an adc result at the maximum or minimum code values (i.e., 0000 hex or ffff hex for unipolar mode and 8000 hex and 7fff hex for bipolar mode). the power-on default is 0. reading the status register does not clear the adou bit. sdc: signal-detect comparator status bit. when sdc = 1, the positive input to the signal-detect compara- tor exceeds the negative input plus the programmed threshold voltage. the sdc bit clears during the status register read unless the condition remains true. the sdc bit also deasserts when the signal-detect comparator powers down (sdce = 0). the power-on default is 0. crdy: high-frequency-clock ready status bit. crdy = 1 indicates a locked high-frequency clock to the 32khz reference frequency by the fll. the crdy bit clears during the status register read. this bit only asserts after power-up or after enabling the fll using the flle bit. the power-on default is 0. add: adc-done status bit. add = 1 indicates a com- pleted adc conversion or calibration. clear the add bit by reading the appropriate adc data, offset, or gain-cali- bration registers. the adc status bit also clears when a new adc result updates to the data or calibration regis- ters (i.e., it follows the assertion level of the upio = drdy signal). reading the status register does not clear this bit. this bit is equivalent to the drdy signal available through upio_. the power-on default is 0. hysteresis helps eliminate chatter when running directly off unregulated batteries. if dv dd falls below +1.3v (typ), the power-on reset circuitry is enabled and the hyse bit is deasserted setting the hysteresis back to +20mv. the power-on default is 0. rste: reset output enable bit. set rste = 1 to enable reset to be controlled by the +1.8v dv dd low- supply-voltage detector, and set rste = 0 to disable this control. the power-on default is 1. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 59 ald: alarm (day) status bit. ald = 1 when the value programmed in asec<19:0> in the al_day register matches sec<19:0> in the rtc register. clear the ald bit by reading the status register or by disabling the day alarm (ade = 0). the power-on default is 0. upr<4:1>: user-programmable i/o rising-edge status bits. upr_ = 1 indicates a rising edge on the respec- tive upio_ pin has occurred. clear upr_ by reading the status register. rising edges are detected inde- pendent of upio_ configuration, providing the ability to capture and record rising input (e.g., wu) or output (e.g., pwm) edge events on the upio_. set the appro- priate mask to determine if the edge will generate an interrupt on int. if the upio_ is configured as an out- put, int provides confirmation that an intended rising edge output occurred and has reached the desired dv dd or cpout level (i.e., was not loaded down exter- nally). the power-on default is 0. upf<4:1>: user-programmable i/o falling-edge status bit. upf_ = 1 indicates a falling edge on the respective upio_ has occurred. clear upf_ by reading the status register. falling edges are detected indepen- dent of upio_ configuration, providing the ability to cap- ture and record falling input (e.g., wu) or output (e.g., pwm) edge events on the upio_. set the appropriate mask to determine if that edge should generate an inter- rupt on the int pin. if the upio is configured as an out- put, int provides confirmation that an intended falling edge output occurred at the pin and it reached the desired dgnd level. the power-on default is 0. applications information analog filtering the internal digital filter does not provide rejection close to the harmonics of the modulator sample fre- quency. however, due to high oversampling ratios in the MAX1358B, these bands typically occupy a small fraction of the spectrum and most broadband noise is filtered. therefore, the analog filtering requirements in front of the MAX1358B are considerably reduced com- pared to a conventional converter with no on-chip filter- ing. in addition, because the device? common-mode rejection (60db) extends out to several khz, the com- mon-mode noise susceptibility in this frequency range is substantially reduced. depending on the application, provide filtering prior to the MAX1358B to eliminate unwanted frequencies the digital filter does not reject. providing additional filtering in some applications ensures that differential noise signals outside the frequency band of interest do not saturate the analog modulator. when placing passive components in front of the MAX1358B, ensure a low enough source impedance to prevent introducing gain errors to the system. this con- figuration significantly limits the amount of passive anti- aliasing filtering that can be applied in front of the MAX1358B. see table 3 for acceptable source imped- ances. power-on reset or power-up after a power-on reset, the dv dd voltage supervisor is enabled and all upios are configured as inputs with pullups enabled. the internal oscillators are enabled and are output at clk and clk32k once the dv dd voltage supervisor is cleared and the subsequent timeout period has expired. all interrupts are masked except crdy. figure 19 illustrates the timing of various signals during initial power-up, sleep mode, and wake-up events. the adc, charge pump, internal reference, op amp(s), dac, and switches are disabled after power-up. power modes two power modes are available for the MAX1358B: sleep and normal mode. in sleep mode, all functional blocks are powered down except the serial interface, data registers, internal bandgap, wake-up circuitry (if enabled), dv dd voltage supervisor (if enabled), and the 32khz oscillator (if enabled), which remain active. see table 15 for details of the sleep-mode and normal- mode power states of the various internal blocks. each analog block can be shut down individually through its respective control register with the excep- tion of the bandgap reference. sleep mode sleep mode is entered one of three ways: writing to the sleep register address. the result is the shdn bit is set to 1. asserting the sleep or sleep function on a upio (sleep takes precedence over software writes or wake-up events). the shdn bit is unaffected. asserting the shdn bit by writing slp = 1 in the sleep_cfg register. entering sleep mode is an or function of the upio or shdn bit. before entering sleep mode, configure the normal mode conditions. exit sleep mode and enter normal mode by one of the following methods: with the shdn bit = 0, deassert the sleep or sleep function on upio, only if sleep or sleep function is used for entering sleep mode. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 60 ______________________________________________________________________________________ internal low dv dd detector output disabled, but pulled low output enabled sclk, din cs dout internal drdy upio (pwm) connected to power supply shdn pin int upio (shdn) upio (wu) (int. pullup) ck32k (32khz) sck32e = 0 buffer disabled ck32e = 1 ck32e = 1 xin, xout (32khz) sosce = 1 osce = 1 osce = 1 por dv dd 1.8v av dd 1.8v reset (open drain) internal external internal crdy hfce = 1, flle = 1 clk lo hi lo hi lo hi lo hi lo hi lo hi lo hi lo hi lo hi lo hi lo hi lo hi 0v 1 2 0v 1 2 lo hi lo hi lo hi sleep write three-stated spwme = 1 pwme = 0 pwme = 0 power supply off power supply off t dpu t dfi t dfi internal t wu t dfon t dfon t dfof t dpd internal if flle = 0, crdy will stay low, dfon = 0 initial power, wake-up, and sleep xtal between 32kin and 32kout pin figure 19. initial power-up, sleep mode, and wake-up timing diagram with av dd > 1.8v datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 61 with the sleep or sleep function deasserted on upio, clear the shdn bit by writing to the normal- mode register address control byte. with the sleep or sleep function deasserted, assert wu or wu (wake-up) function on upio. with the sleep or sleep function deasserted, the day alarm triggers. wake-up a wake-up event, such as an assertion of a upio con- figured as wu or a time-of-day alarm causes the MAX1358B to exit sleep mode, if in sleep mode. a wake-up event in normal mode results only in a wake-up event being recorded in the status register. reset the reset output pulls low for any one of the following cases: power-on reset, dv dd monitor trips and rste = 0, watchdog timer expires, crystal oscillator is attached, and 32khz clock not ready. the reset output can be turned off through the rste bit in the ps_vmons register, causing dv dd low sup- ply voltage events to issue an interrupt or poll through the ldvd status bit. this allows brownout detection ?s that operate with dv dd < 1.8v. driving upio outputs to av dd levels upio outputs can be driven to av dd levels in systems with separate av dd and dv dd supplies. disable the charge-pump doubler by setting cpe = 0 in the ps_vmons register, and connect the system? analog supply to av dd and cpout. setting upio outputs to drive to cpout results in av dd -referenced logic levels. supply voltage measurement the av dd supply voltage can be measured with the adc by reversing the normal input and reference sig- nals. the ref voltage is applied to one multiplexer input, and agnd is selected in the other. the av dd signal is then switched in as the adc reference voltage and a conversion is performed. the av dd value can then be calculated directly as: v avdd = (v ref x gain x 65,536)/n where v ref is the reference voltage for the adc, gain is the pga gain before the adc, and n is the adc result. note the av dd voltage must be greater than the gained-up ref voltage (av dd > v ref x gain). this measurement must be done in unipolar mode. 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0010 65,535 65,533 input voltage (lsb) binary output code 1111 1111 1111 1101 1111 1111 1111 1110 1111 1111 1111 1111 1 lsb = v ref (gain x 65,536) 0 2 v ref /gain v ref /gain 13 1111 1111 1111 1100 0000 0000 0000 0011 full-scale transition figure 20. adc unipolar transfer function MAX1358B dac a outa outb ref dac b fba fbb figure 22. dac unipolar output circuit 0+1 -1 1000 0000 0000 0000 1000 0000 0000 0001 1000 0000 0000 0010 +32,767 +32,765 input voltage (lsb) binary output code 0111 1111 1111 1101 0111 1111 1111 1110 0111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0001 1111 1111 1111 1111 1 lsb = v ref (gain x 65,536) x 2 -32,768 -32,766 v ref /gain v ref /gain v ref /gain v ref /gain figure 21. adc bipolar transfer function datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 62 ______________________________________________________________________________________ power supplies av dd and dv dd provide power to the MAX1358B. the av dd powers up the analog section, while the dv dd pow- ers up the digital section. the power supply for both av dd and dv dd ranges from +1.8v to +3.6v. both av dd and dv dd must be greater than +1.8v for device operation. av dd and dv dd can connect to the same power supply. bypass av dd to agnd with a 10? electrolytic capacitor in parallel with a 0.1? ceramic capacitor, and bypass dv dd to dgnd with a 10? electrolytic capacitor in paral- lel with a 0.1? ceramic capacitor. for improved perfor- mance, place the bypass capacitors as close to the device as possible. adc transfer functions figures 20 and 21 provide the adc transfer functions for unipolar and bipolar mode. the digital output code format is binary for unipolar mode and two? comple- ment for bipolar mode. calculate 1 lsb using the fol- lowing equations: 1 lsb (unipolar mode) = v ref /(gain x 65,536) 1 lsb (bipolar mode) = ?v ref /(gain x 65,536) where v ref equals the reference voltage at ref and gain equals the pga gain. in unipolar mode, the output code ranges from 0 to 65,535 for inputs from zero to full-scale. in bipolar mode, the output code ranges from -32,768 to +32,767 for inputs from negative full-scale to positive full-scale. dac unipolar output for a unipolar output, the output voltages and the refer- ence have the same polarity. figure 22 shows the unipolar output circuit of the MAX1358B, which is also the typical operating circuit for the dac. table 22 lists some unipolar input codes and their corresponding output voltages. for larger output swing, see figure 23. this circuit shows the output amplifiers configured with a closed- loop gain of +2v/v to provide 0 to 2.5v full-scale range with the 1.25v reference. dac bipolar output the MAX1358B dac output can be configured for bipolar operation using the application circuit in figure 24: where n is the decimal value of the dac? binary input code. table 23 shows digital codes (offset binary) and corre- sponding output voltages for figure 24 assuming r 1 = r 2 . vv n out ref = ? ? ? ? ? ? ? ? ? ? ? ? ? 2 1024 1 MAX1358B dac a outa outb v ref = 1.25v ref dac b fba 10k ? 10k ? 10k ? 10k ? fbb r 2 r 2 = r 1 r 1 MAX1358B dac_ out_ v out +3.3v -3.3v fb_ v ref = 1.25v v ref figure 24. dac bipolar output circuit figure 23. dac unipolar rail-to-rail output circuit dac contents msb lsb analog output 1111 1111 11 +v ref (1023/1024) 1000 0000 01 +v ref (513/1024) 1000 0000 00 +v ref (512/1024) = +v ref /2 0111 1111 11 +v ref (511/1024) 0000 0000 01 +v ref (1/1024) 0000 0000 00 0 table 22. unipolar code dac contents msb lsb analog output 1111 1111 11 +v ref (511/512) 1000 0000 01 +v ref (1/512) 1000 0000 00 0 0111 1111 11 -v ref (1/512) 0000 0000 01 -v ref (511/512) 0000 0000 00 -v ref (512/512) = -v ref table 23. bipolar code datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 63 MAX1358B 32kin 100k ? cmos clock (0 to dv dd ) 100k ? figure 25. clocking with a cmos signal MAX1358B upio1 gpion ain1 x2 v ref = 1.25v battvcheck < 0.6125v v batt1 backlight v dd note: gpion is low = led on, high-z = led off p v batt2 figure 26. input multiplexer clocking with a cmos signal a cmos signal can be used to drive 32kin if it is divid- ed down. figure 25 is an example circuit, which works well. input multiplexer the mux inputs can range between agnd and av dd . however, when the internal temperature sensor is enabled, ain1 and ain2 cannot exceed 0.7v. this necessitates additional circuitry to divide down the input signal. see figure 26 for an example circuit that divides down backlight v dd to work properly with the ain1 pin. optical reflectometry application with dual led and single photodiode figure 27 illustrates the MAX1358B in a complete opti- cal reflectometry application with two transmitting leds and one receiving photodiode. the leds transmit light at a specific wavelength onto the sample strip, and the photodiode receives the reflections from the strip. set the dac to provide appropriate bias currents for the leds. always keep the photodiodes reverse-biased or zero-biased. spdt1 and spdt2 switch between the two leds. electrochemical sensor operation the MAX1358B family interface with electrochemical sensors. the 10-bit dac with the force-sense buffers have the flexibility to connect to many different types of sensors. an external precision resistor completes the transimpedance amplifier configuration to convert the current generated by the sensor to a voltage measure- ment using the adc. the induced error from this source is negligible due to fba? extremely low input bias cur- rent. internally, the adc can differentially measure directly across the external transimpedance resistor, rf, eliminating any errors due to voltages drifting over time, temperature, or supply voltage. temperature measurement with two remote sensors use two diode-connected 2n3904 transistors for exter- nal temperature sensing in figure 29. select ain1 and ain2 through the positive and negative mux, respec- tively. for internal temperature sensor measurements, set muxp<3:0> to 0111, and set muxn<3:0> to 0000. the analog input signals feed through a pga to the adc for conversion. the MAX1358B integrated pwm is available for lcd bias control, sensor-bias voltage trimming, buzzer drive, and duty-cycled sleep-mode power-control schemes. figure 30 shows the MAX1358B performing lcd bias control. a sensor-bias voltage trimming application is shown in figure 31. figures 33 and 34 show the pwm circuitry being used in a single-ended and differential piezoelectric buzzer-driving application. adc calibration internal to the MAX1358B, the adc is 24 bits and is always in bipolar mode. the offset cal and gain cal data is also 24 bits. the conversion to unipolar and the gain are performed digitally. the default values for the offset cal and gain cal registers in the MAX1358B are 00 0000h and 80 0000h, respectively. the calibration works as follows: adc = (raw - offset) x gain x pga where adc is the conversion result in the data register, raw is the output of the decimation filter internal to the MAX1358B, offset is the value stored in the offset cal register, gain is the value stored in the gain cal register, and pga is the selected pga gain found in the adc register as gain<1:0>. in unipolar mode, all nega- tive values return a zero result and an additional gain of 2 is added. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 64 ______________________________________________________________________________________ c down up mem v ss input input input upio2 upio1 upio3 upio4 MAX1358B din dout sclk cs reset int clk clk32k av dd dv dd test strip v ss agnd dgnd 32kin 32kout 32.768khz linear reg dv dd charge- pump doubler v ss reg cf+ cf- cpout v ss v bat 2 aaa or 1 lithium coin cell v ss v ss v dd cs2 reset input x2in 32kin eeprom v ss v bat gnd v cc cs si sck so serial-port interface v ss cs1 sck miso mosi v ss v cp v ss txd rxd v cp high-frequency micro clock 32khz micro clock lcd module bdin bdout bsclk bcs2 v ss v cp in1- in1+ out1 v ss adc pwm daca ref bg led v cp v cp led ambient light led sources snc1 scm1 sno1 fba v ss swa outa ain1 ain2 scm2 snc2 sno2 v ss 1nf v ss cs2 figure 27. optical reflectometry application with dual led and single photodiode datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 65 v cp v ss lcdbias lcd drivers c down up mem v ss input input input upio2 upio1 upio3 upio4 outa swa fba out1 in1- in1+ ain1 ain2 ref MAX1358B pwm cpout cpout din dout sclk cs reset int clk clk32k av dd dv dd v ss test strip strip inserted piezo alarm v ss lcdbias v ss remote temperature- measurement diode agnd dgnd 32kin 32kout adc bg 32.768khz linear reg dv dd charge- pump doubler v ss reg cf+ cf- cpout v ss v bat 2 aaa or 1 lithium coin cell v ss v ss v dd txd cs2 reset input eeprom v ss v bat gnd v cc cs si sck so serial-port interface v ss cs1 sck miso mosi v ss seg<23:0> com<3:0> rxd v cp high-frequency micro clock 32khz micro clock lcd gla ss buz_lo buz_hi rx_wakeup rx_wakeup sno2 scm2 snc2 v ss daca outb swb fbb dacb sno1 scm1 snc1 cs2 x2in 32kin figure 28. electrochemical meter application circuit (traditional and counter configuration) datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 66 ______________________________________________________________________________________ for self-calibration, the offset value is the raw result when the inputs are shorted internally and the gain value is 1/(raw - offset) with the reference connected to the input. this is done automatically when these modes are selected. the self-offset and gain calibration corrects for errors internal to the adc and the results are stored and used automatically in the offset cal and gain cal registers. for best results, use the adc in the same con- figuration as the calibration. this pertains to conversion rate only because the pga gain and unipolar/bipolar modes are performed digitally. for system calibration, the offset and gain values cor- rect for errors in the whole signal path including the internal adc and any external circuits in the signal path. for the system calibration, a user-provided zero- input condition is required for the offset calibration and a user-provided full-scale input is required for the gain calibration. these values are automatically written to the offset cal and gain cal registers. the order of the calibrations should be offset followed by gain. the offset correction value is in two? complement. the default value is 000000h, 00...00b, or 0 decimal. the gain correction value is an unsigned binary number with 23 bits to the right of the decimal point. the largest number is therefore 1.1111...1b = 2 - 2 -23 and the small- est is 0.000...0b = 0, although it does not make sense to use a number smaller than 0.1000...0b = 0.5. the default value is 800000h, 1.000...0b or 1 decimal. changing the offset or gain calibration values does not affect the value in the data register until a new conver- sion has completed. this applies to all the mode bits for pga gain, unipolar/bipolar, etc. grounding and layout for best performance, use a pcb with separate analog and digital ground planes. design the pcb so that the analog and digital sections are separated and confined to different areas of the board. join the digital and analog ground planes at one point. if the das is the only device requiring an agnd-to- dgnd connection, connect planes to the agnd pin of the das. in systems where multiple devices require agnd-to- dgnd connections, the connection should still be made at only one point. make the star ground as close as possi- ble to the MAX1358B. avoid running digital lines under the device because these may couple noise onto the device. run the ana- log ground plane under the MAX1358B to minimize coupling of digital noise. make the power-supply lines to the MAX1358B as wide as possible to provide low- impedance paths and reduce the effects of glitches on the power-supply line. shield fast-switching signals such as clocks with digital ground to avoid radiating noise to other sections of the board. avoid running clock signals near the analog inputs. avoid crossover of digital and analog signals. good decoupling is important when using high-resolu- tion adcs. decouple all analog supplies with 10? capacitors in parallel with 0.1? hf ceramic capacitors to agnd. place these components as close to the device as possible to achieve the best decoupling. crystal layout follow basic layout guidelines when placing a crystal on a pcb with a das to avoid coupled noise: 1) place the crystal as close as possible to 32kin and 32kout. keeping the trace lengths between the crystal and inputs as short as possible reduces the probability of noise coupling by reducing the length of the ?ntennae? keep the 32kin and 32kout lines close to each other to minimize the loop area of the clock lines. keeping the trace lengths short also decreases the amount of stray capacitance. 2) keep the crystal solder pads and trace width to 32kin and 32kout as small as possible. the larg- er these bond pads and traces are, the more likely it is that noise will couple from adjacent signals. 3) place a guard ring (connect to ground) around the crystal to isolate the crystal from noise coupled from adjacent signals. 4) ensure that no signals on other pcb layers run directly below the crystal or below the traces to 32kin and 32kout. the more the crystal is isolat- ed from other signals on the board, the less likely it is that noise will be coupled into the crystal. maintain a minimum distance of 5mm between any digital signal and any trace connected to 32kin or 32kout. 5) place a local ground plane on the pcb layer imme- diately below the crystal guard ring. this helps to isolate the crystal from noise coupling from signals on other pcb layers. note: the ground plane must be in the vicinity of the crystal only and not on the entire board. datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 67 parameter definitions inl integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line is either a best-straight-line fit or a line drawn between the end points of the transfer function, once off- set and gain errors have been nulled. inl for the MAX1358B is measured using the end-point method. dnl differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of greater than -1 lsb guarantees no missing codes and a monotonic transfer function. gain error gain error is the amount of deviation between the mea- sured full-scale transition point and the ideal full-scale transition point. common-mode rejection common-mode rejection (cmr) is the ability of a device to reject a signal that is common to both input terminals. the common-mode signal can be either an ac or a dc signal or a combination of the two. cmr is often expressed in decibels. power-supply rejection ratio (psrr) power-supply rejection ratio (psrr) is the ratio of the input supply change (in volts) to the change in the converter output (in volts). it is typically measured in decibels. a v = 1, 2, 4, 8 a v = 1, 1.638, 2 MAX1358B pga mux 2n3904 16-bit adc c ref ref ref mux temp sensor ain1 agnd ain2 agnd 2n3904 1.25v ref figure 29. temperature measurement with two remote sensors datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 68 ______________________________________________________________________________________ ref sno1 scm1 snc1 agnd spdt1 pwm in1+ in1- out1 transducer 0.300v ( 1mv) i t 0.1 f 60k ? ~0.3v 240k ? 350k ? ~19khz voltage ripple < 1mv ~1.25v MAX1358B figure 31. sensor-bias voltage trim application (1.8v to 2.6v) 0.01 f c mux sv_ alh_ upio_ lcd drivers seg lcd com n m cpout 200k ? 100k ? 100k ? 100k ? 100k ? pwm dv dd cpout en_ MAX1358B figure 30. lcd contrast-adjustment application datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor ______________________________________________________________________________________ 69 shdn pwm alh_ upio_ sv_ dv dd cpout mux MAX1358B v in v out power supply av dd v dd c 100 f < 10 a v dd psctl v batt dv dd on-time <100ms typ 10s period typ +3.3v v dd +2.3v psctl en_ 10m ? figure 32. power-supply sleep-mode duty-cycle control pwm alh_ upio_ sv_ dv dd cpout mux 1k ? 0v cpout(+3.2v) 1khz to 8khz typ ~10,000pf MAX1358B figure 33. single-ended piezoelectric buzzer drive datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor 70 ______________________________________________________________________________________ chip information process: bicmos MAX1358B mux sv_ alh_ upio_ 1k ? pwm dv dd cpout mux sv_ alh_ upio_ 1k ? dv dd cpout 0v 0v cpout(+3.2v) cpout + 6.4v diff - -cpout cpout(~+3.2v) 1khz to 8khz typ 1khz to 8khz typ ~10,000pf figure 34. differential piezoelectric buzzer drive package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 40 tqfn-ep t4066+5 21-0141 90-0055 datasheet.in
MAX1358B 16-bit, data-acquisition system with adc, dacs, upios, rtc, voltage monitors, and temp sensor maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 71 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 8/10 initial release of data sheet. the MAX1358B previously appeared on a different data sheet. 1?0 datasheet.in

▲Up To Search▲

Price & Availability of MAX1358B

	To Download MAX1358B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .